LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 500

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 427. DMA Status register (DMA_STAT, address 0x4001 1014) bit description
<Document ID>
User manual
Bit
0
1
2
3
4
5
6
Symbol
TI
TPS
TU
TJT
OVF
UNF
RI
22.6.22 DMA Status register
Description
Transmit interrupt
This bit indicates that frame transmission is finished and TDES1[31] is set in the First
Descriptor.
Transmit process stopped
This bit is set when the transmission is stopped.
Transmit buffer unavailable
This bit indicates that the Next Descriptor in the Transmit List is owned by the host
and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain
the Transmit Process state transitions. To resume processing transmit descriptors,
the host should change the ownership of the bit of the descriptor and then issue a
Transmit Poll Demand command.
Transmit jabber timeout
This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter
had been excessively active. The transmission process is aborted and placed in the
Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert.
Receive overflow
This bit indicates that the Receive Buffer had an Overflow during frame reception. If
the partial frame is transferred to application, the overflow status is set in RDES0[11].
Transmit underflow
This bit indicates that the Transmit Buffer had an Underflow during frame
transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.
Receive interrupt
This bit indicates the completion of frame reception. Specific frame status information
has been posted in the descriptor. Reception remains in the Running state.
Table 426. DMA Transmit descriptor list address register (DMA_TRANS_DES_ADDR,
The Status register contains all the status bits that the DMA reports to the host. This
register is usually read by the Software driver during an interrupt service routine or polling.
Most of the fields in this register cause the host to be interrupted. The bits in this register
are not cleared when read. Writing 1 to (unreserved) bits in this register (bits [16:0]) clears
them and writing 0 has no effect. Each field (bits[16:0]) can be masked by masking the
appropriate bit in the DMA_INT_EN register.
Bit
31:0
Symbol
SRL
address 0x4001 1010) bit description
All information provided in this document is subject to legal disclaimers.
Description
Start of transmit list
This field contains the base address of the First Descriptor
in the Transmit Descriptor list. The LSB bits [1/2/3:0] for
32/64/128-bit bus width) will be ignored and taken as
all-zero by the DMA internally. Hence these LSB bits are
Read Only.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
Reset
value
0
0
0
0
0
0
0
500 of 1164
Access
R/W
Access
R/SS/
WC
R/SS/
WC
R/SS/
WC
R/SS/
WC
R/SS/
WC
R/SS/
WC
R/SS/
WC