LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 714

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 663. Register overview: UART0/2/3 (base address: 0x4008 1000, 0x400C 1000, 0x400C
Name
IIR
FCR
LCR
-
LSR
-
SCR
ACR
ICR
FDR
-
HDEN
-
SCICTRL
RS485CTRL
RS485ADRMA
TCH
RS485DLY
SYNCCTRL
TER
2000)
All information provided in this document is subject to legal disclaimers.
Access Address
RO
WO
R/W
-
RO
-
R/W
R/W
R/W
R/W
-
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 00.13 — 20 July 2011
offset
0x008
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C -
0x03C
0x040
0x044
0x048
0x04C
0x050
0x054
0x058
0x05C
Description
Interrupt ID Register. Identifies which interrupt(s) are
pending.
FIFO Control Register. Controls UART FIFO usage
and modes.
Line Control Register. Contains controls for frame
formatting and break generation.
Reserved
Line Status Register. Contains flags for transmit and
receive status, including line errors.
Reserved
Scratch Pad Register. Eight-bit temporary storage
for software.
Auto-baud Control Register. Contains controls for
the auto-baud feature.
IrDA control register (UART3 only)
Fractional Divider Register. Generates a clock input
for the baud rate divider.
Reserved
Half-duplex enable Register
Reserved
Smart card interface control register
RS-485/EIA-485 Control. Contains controls to
configure various aspects of RS-485/EIA-485
modes.
RS-485/EIA-485 address match. Contains the
address match value for RS-485/EIA-485 mode.
RS-485/EIA-485 direction control delay.
Synchronous mode control register.
Transmit Enable Register. Turns off UART
transmitter for use with software flow control.
Chapter 32: LPC18xx USART0_2_3
UM10430
© NXP B.V. 2011. All rights reserved.
714 of 1164
Reset
value
0x01
0x00
0x00
-
0x60
-
0x00
0x00
0x00
0x10
-
-
0x00
0x00
0x00
0x00
0x01