LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 811

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 752. Register overview: C_CAN1 (base address 0x400A 4000)
Name
BRPE
-
IF1_CMDREQ
IF1_CMDMSK_W
IF1_CMDMSK_R
IF1_MSK1
IF1_MSK2
IF1_ARB1
IF1_ARB2
IF1_MCTRL
IF1_DA1
IF1_DA2
IF1_DB1
IF1_DB2
-
IF2_CMDREQ
IF2_CMDMSK
IF2_MSK1
IF2_MSK2
IF2_ARB1
IF2_ARB2
IF2_MCTRL
IF2_DA1
IF2_DA2
IF2_DB1
IF2_DB2
-
TXREQ1
TXREQ2
-
ND1
ND2
-
IR1
IR2
All information provided in this document is subject to legal disclaimers.
RO
RO
Access
-
-
RO
RO
-
-
RO
RO
Rev. 00.13 — 20 July 2011
Address
offset
0x018
0x01C
0x020
0x024
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C -
0x07C
0x080
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C
0x0A0
0x0A4
0x0A8
0x0AC -
0x0FC
0x100
0x104
0x108 -
0x11C
0x120
0x124
0x128 -
0x13C
0x140
0x144
Description
Baud rate prescaler extension register
Reserved
Message interface 1 command request 0x0001
Message interface 1 command mask
(write direction)
Message interface 1 command mask
(read direction)
Message interface 1 mask 1
Message interface 1 mask 2
Message interface 1 arbitration 1
Message interface 1 arbitration 2
Message interface 1 message control
Message interface 1 data A1
Message interface 1 data A2
Message interface 1 data B1
Message interface 1 data B2
Reserved
Message interface 2 command request 0x0001
Message interface 2 command mask
Message interface 2 mask 1
Message interface 2 mask 2
Message interface 2 arbitration 1
Message interface 2 arbitration 2
Message interface 2 message control
Message interface 2 data A1
Message interface 2 data A2
Message interface 2 data B1
Message interface 2 data B2
Transmission request 1
Transmission request 2
Reserved
New data 1
New data 2
Reserved
Interrupt pending 1
Interrupt pending 2
Chapter 36: LPC18xx C_CAN
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0x0000
-
0x0000
0x0000
0xFFFF
0xFFFF
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
0x0000
0xFFFF
0xFFFF
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
0x0000
0x0000
-
0x0000
0x0000
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