LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 854

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
37.4 Applications
37.5 General description
<Document ID>
User manual
Interfaces to external I
other microcontrollers, etc.
A typical I
direction bit (R/W), two types of data transfers are possible on the I
The I
master receiver mode, slave transmitter mode and slave receiver mode.
The I
power off to the processor without interfering with other devices on the same I
Fig 131. I
•
•
Data transfer from a master transmitter to a slave receiver. The first byte transmitted
by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte.
Data transfer from a slave transmitter to a master receiver. The first byte (the slave
address) is transmitted by the master. The slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a “not acknowledge” is returned. The master device generates all
of the serial clock pulses and the START and STOP conditions. A transfer is ended
with a STOP condition or with a Repeated START condition. Since a Repeated
START condition is also the beginning of the next serial transfer, the I
be released.
2
2
C interface is byte oriented and has four operating modes: master transmitter mode,
C interface complies with the entire I
I
2
C bus
2
2
C-bus configuration is shown in
C-bus configuration
SDA
All information provided in this document is subject to legal disclaimers.
LPC18xx
2
Rev. 00.13 — 20 July 2011
C standard parts, such as serial RAMs, LCDs, tone generators,
SCL
pull-up
resistor
OTHER DEVICE WITH
I
2
C INTERFACE
2
Figure
C specification, supporting the ability to turn
Chapter 37: LPC18xx I2C-bus interface
pull-up
resistor
131. Depending on the state of the
OTHER DEVICE WITH
I
2
C INTERFACE
2
C-bus:
UM10430
© NXP B.V. 2011. All rights reserved.
2
C bus will not
2
SDA
SCL
C-bus.
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