LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 639

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 548. Register overview: Motor Control Pulse Width Modulator (MCPWM) (base address 0x400A 0000)
Table 549. MCPWM Control read address (CON - 0x400A 0000) bit description
<Document ID>
User manual
Name
CNTCON_SET
CNTCON_CLR
INTF
INTF_SET
INTF_CLR
CAP_CLR
Bit
0
1
2
3
4
7:5
8
9
Symbol
RUN0
CENTER0
POLA0
DTE0
DISUP0
-
RUN1
CENTER1
26.7.1.1 MCPWM Control read address
26.7.1 MCPWM Control register
Access
WO
WO
RO
WO
WO
WO
Value Description
0
1
0
1
0
1
0
1
0
1
-
0
1
0
1
The CON register controls the operation of all channels of the PWM. This address is
read-only, but the underlying register can be modified by writing to addresses CON_SET
and CON_CLR.
Stops/starts timer channel 0.
Stop.
Run.
Edge/center aligned operation for channel 0.
Edge-aligned.
Center-aligned.
Selects polarity of the MCOA0 and MCOB0 pins.
Passive state is LOW, active state is HIGH.
Passive state is HIGH, active state is LOW.
Controls the dead-time feature for channel 0.
Dead-time disabled.
Dead-time enabled.
Enable/disable updates of functional registers for channel 0 (see
Functional registers are updated from the write registers at the end of each PWM
cycle.
Functional registers remain the same as long as the timer is running.
Reserved.
Stops/starts timer channel 1.
Stop.
Run.
Edge/center aligned operation for channel 1.
Edge-aligned.
Center-aligned.
All information provided in this document is subject to legal disclaimers.
Address
offset
0x060
0x064
0x068
0x06C
0x070
0x074
Rev. 00.13 — 20 July 2011
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
Description
Count Control set address
Count Control clear address
Interrupt flags read address
Interrupt flags set address
Interrupt flags clear address
Capture clear address
Section
UM10430
© NXP B.V. 2011. All rights reserved.
26.8.2).
Reset value
-
-
0
-
-
-
639 of 1164
0
0
0
0
Reset
value
0
0
0