LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 308

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 236. Command Register (CMD, address 0x4000 402C) bit description
<Document ID>
User manual
Bit
22
23
24
25
26
27
28
30:29
31
Symbol
READ_CEATA_DEVICE
CCS_EXPECTED
ENABLE_BOOT
EXPECT_BOOT_ACK
DISABLE_BOOT
BOOT_MODE
VOLT_SWITCH
-
START_CMD
Value
0
1
0
1
0
1
0
1
All information provided in this document is subject to legal disclaimers.
Description
read ceata device. Software should set this bit to indicate that CE-ATA
device is being accessed for read transfer. This bit is used to disable
read data time-out indication while performing CE-ATA read transfers.
Maximum value of I/O transmission delay can be no less than 10
seconds. DWC_mobile_storage should not indicate read data
time-out while waiting for data from CE-ATA device.
Host is not performing read access (RW_REG or RW_BLK) towards
CE-ATA device.
Host is performing read access (RW_REG or RW_BLK) towards
CE-ATA device.
ccs expected. If the command expects Command Completion Signal
(CCS) from the CE-ATA device, the software should set this control
bit. DWC_mobile_storage sets Data Transfer Over (DTO) bit in
RINTSTS register and generates interrupt to host if Data Transfer
Over interrupt is not masked.
Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control
register), or command does not expect CCS from device.
Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK
command expects command completion signal from CE-ATA device.
Enable Boot - this bit should be set only for mandatory boot mode.
When Software sets this bit along with start_cmd, CIU starts the boot
sequence for the corresponding card by asserting the CMD line low.
Do NOT set disable_boot and enable_boot together.
Expect Boot Acknowledge. When Software sets this bit along with
enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0
from the selected card.
Disable Boot. When software sets this bit along with start_cmd, CIU
terminates the boot operation. Do NOT set disable_boot and
enable_boot together.
Boot Mode
Mandatory Boot operation
Alternate Boot operation
Voltage switch bit
No voltage switching
Voltage switching enabled; must be set for CMD11 only
Reserved
Start command. Once command is taken by CIU, bit is cleared. When
bit is set, host should not attempt to write to any command registers. If
write is attempted, hardware lock error is set in raw interrupt register.
Once command is sent and response is received from
SD_MMC_CEATA cards, Command Done bit is set in raw interrupt
register.
Rev. 00.13 — 20 July 2011
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
308 of 1164
Reset
value
0
0
0
0
0
0
0