LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 361

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 302. HCSPARAMS register (HCSPARAMS - address 0x4000 6104) bit description
Table 303. HCCPARAMS register (HCCPARAMS - address 0x4000 6108) bit description
Bit
3:0
4
7:5
11:8
15:12
16
19:17
23:20
27:24
31:28
Bit
0
1
2
Symbol
N_PORTS
PPC
-
PI
N_TT
Symbol
ADC
PFL
ASP
N_PCC
N_CC
-
N_PTT
-
All information provided in this document is subject to legal disclaimers.
Description
64-bit Addressing Capability. If zero, no 64-bit addressing
capability is supported.
Programmable Frame List Flag. If set to one, then the
system software can specify and use a smaller frame list
and configure the host controller via the USBCMD register
Frame List Size field. The frame list must always be
aligned on a 4K-boundary. This requirement ensures that
the frame list is always physically contiguous.
Asynchronous Schedule Park Capability. If this bit is set to
a one, then the host controller supports the park feature
for high-speed queue heads in the Asynchronous
Schedule.The feature can be disabled or enabled and set
to a specific level by using the Asynchronous Schedule
Park Mode Enable and Asynchronous Schedule Park
Mode Count fields in the USBCMD register.
Rev. 00.13 — 20 July 2011
Description
Number of downstream ports. This field specifies
the number of physical downstream ports
implemented on this host controller.
Port Power Control. This field indicates whether
the host controller implementation includes port
power control.
These bits are reserved and should be set to zero. -
Number of Ports per Companion Controller. This
field indicates the number of ports supported per
internal Companion Controller.
Number of Companion Controller. This field
indicates the number of companion controllers
associated with this USB2.0 host controller.
Port indicators. This bit indicates whether the
ports support port indicator control.
These bits are reserved and should be set to zero. -
Number of Ports per Transaction Translator. This
field indicates the number of ports assigned to
each transaction translator within the USB2.0 host
controller.
Number of Transaction Translators. This field
indicates the number of embedded transaction
translators associated with the USB2.0 host
controller.
These bits are reserved and should be set to zero. -
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0x1
0x1
0x0
0x0
0x1
0x0
0x0
Reset
value
0
1
1
361 of 1164
-
-
-
Access
RO
RO
RO
RO
RO
RO
RO
Access
RO
RO
RO