LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 887
LPC1837FET256,551
Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1837FET256,551
Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Details
Other names
935293795551
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Table 824. Miscellaneous States
<Document ID>
User manual
Status
Code
(STAT)
0xF8
0x00
37.10.6.1 Simultaneous Repeated START conditions from two masters
Status of the I
and hardware
No relevant state
information available;
SI = 0.
Bus error during MST
or selected slave
modes, due to an
illegal START or
STOP condition. State
0x00 can also occur
when interference
causes the I
to enter an undefined
state.
37.10.6 Some special cases
2
causes the I
clear the STO flag (no other bits in CON are affected). The SDA and SCL lines are
released (a STOP condition is not transmitted).
The I
during a serial transfer:
A Repeated START condition may be generated in the master transmitter or master
receiver modes. A special case occurs if another master simultaneously generates a
Repeated START condition (see
either master since they were both transmitting the same data.
If the I
a Repeated START condition itself, it will release the bus, and no interrupt request is
generated. If another master frees the bus by generating a STOP condition, the I
will transmit a normal START condition (state 0x08), and a retry of the total serial data
transfer can commence.
C block
•
•
•
•
•
2
C-bus
Simultaneous Repeated START conditions from two masters
Data transfer after loss of arbitration
Forced access to the I
I
Bus error
2
2
C-bus obstructed by a LOW level on SCL or SDA
C hardware has facilities to handle the following special cases that may occur
2
C hardware detects a Repeated START condition on the I
Application software response
To/From DAT
No DAT action
No DAT action
2
C block to enter the “not addressed” slave mode (a defined state) and to
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
2
C-bus
To CON
STA STO SI
0
No CON action
Figure
1
0
144). Until this occurs, arbitration is not lost by
AA
X
Chapter 37: LPC18xx I2C-bus interface
Next action taken by I
Wait or proceed current transfer.
Only the internal hardware is affected in
the MST or addressed SLV modes. In all
cases, the bus is released and the I
block is switched to the not addressed
SLV mode. STO is reset.
2
C-bus before generating
UM10430
© NXP B.V. 2011. All rights reserved.
2
C hardware
887 of 1164
2
C block
2
C
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