LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 94

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
9.7.4.5 Usage notes
9.7.6.1 Features
9.7.5 Fractional divider for the PLL0 (for audio)
9.7.6 PLL1
Table 74.
In order to set up the PLL0, follow these steps:
The PLL0 for audio applications (PLL0 (for audio)) includes an additional fractional
divider.<tbd>
Fout (MHz)
<tbd>
1. Power down the PLL0 by setting bit 1 in the PLL0_CTRL register to 1. This step is
2. Configure the PLL0 m, n, and p divider values in the PLL0_M and PLL0_NP registers.
3. Power up the PLL0 by setting bit 1 in the PLL0_CTRL register to 0.
4. Wait for the PLL0 to lock by monitoring the LOCK bit in the PLL0_STAT register.
5. Enable the PLL0 clock output in the PLL0_CTRL register.
•
•
•
•
•
only needed if the PLL0 is currently enabled.
1 MHz to 50 MHz input frequency. The input from an external crystal is limited to
25 MHz.
9.75 MHz to 320 MHz selectable output frequency with 50% duty cycle.
156 MHz to 320 MHz Current Controlled Oscillator (CCO) frequency.
Power-down mode.
Lock detector.
System PLL divider ratio settings for 12 MHz
All information provided in this document is subject to legal disclaimers.
FCCo (MHz)
<tbd>
Rev. 00.13 — 20 July 2011
Ndec
<tbd>
Chapter 9: LPC18xx Clock Generation Unit (CGU)
Mdec
<tbd>
Pdec
<tbd>
SELR
<tbd>
UM10430
SELI
<tbd>
© NXP B.V. 2011. All rights reserved.
<tbd>
SELP
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