LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 638

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
26.7 Register description
Table 548. Register overview: Motor Control Pulse Width Modulator (MCPWM) (base address 0x400A 0000)
<Document ID>
User manual
Name
CON
CON_SET
CON_CLR
CAPCON
CAPCON_SET
CAPCON_CLR
TC0
TC1
TC2
LIM0
LIM1
LIM2
MAT0
MAT1
MAT2
DT
MCCP
CAP0
CAP1
CAP2
INTEN
INTEN_SET
INTEN_CLR
CNTCON
Access
RO
WO
WO
RO
WO
WO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
WO
WO
RO
Table 547. Pin summary
“Control” registers and “interrupt” registers have separate read, set, and clear addresses.
Reading such a register’s read address (e.g. MCCON) yields the state of the register bits.
Writing ones to the set address (e.g. MCCON_SET) sets register bit(s), and writing ones
to the clear address (e.g. MCCON_CLR) clears register bit(s).
The Capture registers (MCCAP) are read-only, and the write-only MCCAP_CLR address
can be used to clear one or more of them. All the other MCPWM registers (MCTIM,
MCPER, MCPW, MCDEADTIME, and MCCP) are normal read-write registers.
Pin
MCOA0/1/2
MCOB0/1/2
MCABORT
MCI0/1/2
All information provided in this document is subject to legal disclaimers.
Address
offset
0x000
0x004
0x008
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
0x050
0x054
0x058
0x05C
Type
O
O
I
I
0x00C
Rev. 00.13 — 20 July 2011
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
Description
Output A for channels 0, 1, 2
Output B for channels 0, 1, 2
Low-active Fast Abort
Input for channels 0, 1, 2
Description
PWM Control read address
PWM Control set address
PWM Control clear address
Capture Control read address
Capture Control set address
Event Control clear address
Timer Counter register, channel 0
Timer Counter register, channel 1
Timer Counter register, channel 2
Limit register, channel 0
Limit register, channel 1
Limit register, channel 2
Match register, channel 0
Match register, channel 1
Match register, channel 2
Dead time register
Communication Pattern register
Capture register, channel 0
Capture register, channel 1
Capture register, channel 2
Interrupt Enable read address
Interrupt Enable set address
Interrupt Enable clear address
Count Control read address
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0
-
-
0
-
-
0
0
0
0xFFFF FFFF
0xFFFF FFFF
0xFFFF FFFF
0xFFFF FFFF
0xFFFF FFFF
0xFFFF FFFF
0x3FFF FFFF
0
0
0
0
0
-
-
0
638 of 1164