LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1047
LPC1837FET256,551
Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1837FET256,551
Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Details
Other names
935293795551
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42.7.4.1 Pin configuration registers for pins P0_n to PF_n and CLK0 to CLK3
42.7.4.2 Pin configuration register for USB1 pins DP1/DM1
Table 965. Register overview: System Control Unit (SCU) (base address 0x4008 6000)
Each digital pin and each clock pin on the LPC18xx have an associated pin configuration
register which determines the pin’s function and input mode. The allowed functions for
each pin are listed in
Table 966. Pin configuration for pins P0_n to PF_n and CLK0 to CLK3 registers (SFSPY_X,
Remark: The USB_ESEA bit must be set to 1 if USB1 is used.
Table 967. Pin configuration for pins DP1/DM1 register (SFSUSB, address 0x4008 6C80) bit
Name
EMCFBCLKDELAY
EMCADDRDELAY0
EMCADDRDELAY1
EMCADDRDELAY2
-
EMCDINDELAY
Bit
1:0
3:2
31:4
Bit
0
Symbol
USB_AIM
Symbol
SFSP_FUNC
SFSP_MODE
-
address 0x4008 6000 to 0x4008 6C0C) bit description
description
…continued
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
Table
Access
R/W
R/W
R/W
R/W
-
R/W
Rev. 00.13 — 20 July 2011
Value
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
Differential data input AIP/AIM
0 = Going LOW with full speed edge rate
1 = Going HIGH with full speed edge rate
Going LOW with full speed edge rate
Going HIGH with full speed edge rate
963.
Description
Select pin function
Function 0 (default)
Function 1
Function 2
Function 3
Input mode
Pull-up enabled
Repeater mode
Plain input (pull-up/pull-down disabled)
Pull-down enabled
Reserved
Address
offset
0xD10
0xD14
0xD18
0xD1C
0xD20
0xD24
Description
EMC FBCLK delay register
EMC address line delay register 0
EMC address line delay register 1
EMC address line delay register 2
Reserved
EMC data delay register
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
00
00
-
Reset
value
0
1047 of 1164
R/W
Access
R/W
-
Access
R/W
Reset
value
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