LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 646

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
26.7.3 MCPWM Timer/Counter 0-2 registers
26.7.4 MCPWM Limit 0-2 registers
These registers hold the current values of the 32-bit counter/timers for channels 0-2. Each
value is incremented on every PCLK, or by edges on the MCI0-2 pins, as selected by
CNTCON. The timer/counter counts up from 0 until it reaches the value in its
corresponding PER register (or is stopped by writing to CON_CLR).
A TC register can be read at any time. In order to write to the TC register, its channel must
be stopped. If not, the write will not take place, no exception is generated.
Table 555. MCPWM Timer/Counter 0 to 2 registers (TC - 0x400A 0018 (TC0), 0x400A 001C
These registers hold the limiting values for timer/counters 0-2. When a timer/counter
reaches its corresponding limiting value: 1) in edge-aligned mode, it is reset and starts
over at 0; 2) in center-aligned mode, it begins counting down until it reaches 0, at which
time it begins counting up again.
If the channel’s CENTER bit in CON is 0 selecting edge-aligned mode, the match between
TC and LIM switches the channel’s A output from “active” to “passive” state. If the
channel’s CENTER and DTE bits in CON are both 0, the match simultaneously switches
the channel’s B output from “passive” to “active” state.
If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s
deadtime counter to begin counting -- when the deadtime counter expires, the channel’s B
output switches from “passive” to “active” state.
In center-aligned mode, matches between a channel’s TC and LIM registers have no
effect on its A and B outputs.
Writing to either a Limit or a Match (26.7.5) register loads a “write” register, and if the
channel is stopped it also loads an “operating” register that is compared to the TC. If the
channel is running and its “disable update” bit in CON is 0, the operating registers are
loaded from the write registers: 1) in edge-aligned mode, when the TC matches the
operating Limit register; 2) in center-aligned mode, when the TC counts back down to 0. If
the channel is running and the “disable update” bit is 1, the operating registers are not
loaded from the write registers until software stops the channel.
Reading an LIM address always returns the operating value.
Table 556. MCPWM Limit 0 to 2 registers (LIM - 0x400A 0024 (LIM0), 0x400A 0028 (LIM1),
Remark: In timer mode, the period of a channel’s modulated MCO outputs is determined
by its Limit register, and the pulse width at the start of the period is determined by its
Match register. If it suits your way of thinking, consider the Limit register to be the “Period
register” and the Match register to be the “Pulse Width register”.
Bit
31:0
Bit
31:0
Symbol
MCTC
Symbol
MCLIM
(TC1), 0x400A 0020) (TC2)bit description
0x400A 002C (LIM2)) bit description
All information provided in this document is subject to legal disclaimers.
Description
Timer/Counter value.
Description
Limit value.
Rev. 00.13 — 20 July 2011
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
UM10430
© NXP B.V. 2011. All rights reserved.
0xFFFF FFFF
Reset value
Reset
value
0
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