LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 492

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 414. MAC PMT control and status register (MAC_PMT_CTRL_STAT, address 0x4001 002C) bit description
<Document ID>
User manual
Bit
0
1
2
4:3
5
6
8:7
9
30:10
31
Symbol
PD
MPE
WFE
-
MPR
WFR
-
GU
-
WFFRPR Wake-up Frame Filter Register Pointer Reset
22.6.12 MAC Interrupt status register
22.6.11 MAC PMT control and status register
Description
Power-down
When set, all received frames will be dropped. This bit is cleared automatically when
a magic packet or Wake-Up frame is received, and Power-Down mode is disabled.
Frames received after this bit is cleared are forwarded to the application.This bit must
only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set
high.
Magic packet enable
When set, enables generation of a power management event due to Magic Packet
reception.
Wake-up frame enable
When set, enables generation of a power management event due to wake-up frame
reception.
Reserved
Magic Packet Received
When set, this bit indicates the power management event was generated by the
reception of a Magic Packet. This bit is cleared by a Read into this register.
Wake-up Frame Received
When set, this bit indicates the power management event was generated due to
reception of a wake-up frame. This bit is cleared by a Read into this register.
Reserved
Global Unicast
When set, enables any unicast packet filtered by the MAC (DAF) address recognition
to be a wake-up frame.
Reserved
When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is
automatically cleared after 1 clock cycle.
Table 413. MAC Remote wake-up frame filter register (MAC_RWAKE_FRFLT, address 0x4001
The PMT control and status registers programs the request wake-up events and monitors
the wake-up events. See
The Interrupt Status register contents identify the events in the MAC-CORE that can
generate interrupt.
Bit
31:0
Symbol
ADDR
0028) bit description
All information provided in this document is subject to legal disclaimers.
Description
WKUPFMFILTER address
Rev. 00.13 — 20 July 2011
Section 22.7.1
for details.
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
00
0
0
0
0
0x00
0000
0
Reset
value
-
492 of 1164
Access
R/WS/
SC
R/W
R/W
RO
R/SS/R
C
R/SS/R
C
RO
R/W
RO
R/WS/
SC
Access
R/W