LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 565

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
23.7.2 Dual DMA FIFOs and associated control logic
23.7.3 Pixel serializer
In dual panel mode, the DMA FIFOs are filled up in an alternating fashion via a single
DMA request. In single panel mode, the DMA FIFOs are filled up in a sequential fashion
from a single DMA request.
The inherent AHB master interface state machine performs the following functions:
The pixel data accessed from memory is buffered by two DMA FIFOs that can be
independently controlled to cover single and dual-panel LCD types. Each FIFO is 16
words deep by 64 bits wide and can be cascaded to form an effective 32-Dword deep
FIFO in single panel mode.
Synchronization logic transfers the pixel data from the AHB clock domain to the LCD
controller clock domain. The water level marks in each FIFO are set such that each FIFO
requests data when at least four locations become available.
An interrupt signal is asserted if an attempt is made to read either of the two DMA FIFOs
when they are empty (an underflow condition has occurred).
This block reads the 32-bit wide LCD data from the output port of the DMA FIFO and
extracts 24, 16, 8, 4, 2, or 1 bpp data, depending on the current mode of operation. The
LCD controller supports big-endian, little-endian, and Windows CE data formats.
Depending on the mode of operation, the extracted data can be used to point to a color or
gray scale value in the palette RAM or can actually be a true color value that can be
directly applied to an LCD panel input.
Table 481
corresponding to the endianness and bpp combinations. For each of the three supported
data formats, the required data for each panel display pixel must be extracted from the
data word.
•
•
•
•
•
•
•
•
Loads the upper panel base address into the AHB address incrementer on
recognition of a new frame.
Monitors both the upper and lower DMA FIFO levels and asserts a DMA request to
request display data from memory, filling them to above the programmed watermark.
the DMA request is reasserted when there are at least four locations available in
either FIFO (dual panel mode).
Checks for 1 kB boundaries during fixed-length bursts, appropriately adjusting the
address in such occurrences.
Generates the address sequences for fixed-length and undefined bursts.
Controls the handshaking between the memory and DMA FIFOs. It inserts busy
cycles if the FIFOs have not completed their synchronization and updating sequence.
Fills up the DMA FIFOs, in dual panel mode, in an alternating fashion from a single
DMA request.
Asserts the a bus error interrupt if an error occurs during an active burst.
Responds to retry commands by restarting the failed access. This introduces some
busy cycles while it re-synchronizes.
through
All information provided in this document is subject to legal disclaimers.
Table 483
Rev. 00.13 — 20 July 2011
show the structure of the data in each DMA FIFO word
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
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