LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 606

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
24.6.17 SCT conflict enable register
24.6.18 SCT conflict flag register
24.6.19 SCT match registers 0 to 15 (REGMODEn bit = 0)
This register enables the “no change conflict” events specified in the SCT conflict
resolution register to request an IRQ.
Table 517. SCT conflict enable register (CONEN - address 0x4000 00F8) bit description
This register records interrupt-enabled no-change conflict events and provides details of a
bus error. Writing ones to the NCFLAG bits clears the corresponding read bits and will
negate the SCT’s interrupt request if all enabled Flag bits are then zero.
Table 518. SCT conflict flag register (CONFLAG - address 0x4000 00FC) bit description
Match registers are compared to the counter(s) to help create events. When the UNIFY bit
is 0, the L and H registers are independently compared to the L and H counters. When
UNIFY is 1, the L and H registers hold a 32-bit value that is compared to the unified
counter. A Match can only occur in a clock in which the counter is running (STOP and
HALT are both 0).
Match registers can be read at any time. Writing to a Match register while the associated
counter is running will not affect the Match register and will result in an bus error. Match
events occur in the SCT clock in which the counter is (or would be) incremented to the
next value. When a Match event limits its counter as described in
value in the Match register is the last value of the counter before it is cleared to zero (or
decremented if BIDIR is 1).
Bit
15:0
31:16
Bit
15:0
29:16
30
31
Symbol Description
NCEN
-
Symbol
NCFLAG
-
BUSERRL
BUSERRH
All information provided in this document is subject to legal disclaimers.
The SCT requests interrupt when bit n of this register and the SCT
conflict flag register are both one (output 0 = bit 0, output 1 = bit
1,..., output 15 = bit 15).
Reserved
Rev. 00.13 — 20 July 2011
Description
Bit n is one if a no-change conflict event occurred on output n
since reset or a 1 was last written to this bit (output 0 = bit 0,
output 1 = bit 1,..., output 15 = bit 15).
Reserved.
The most recent bus error from this SCT involved writing CTR
L/Unified, STATE L/Unified, MATCH L/Unified, or the Output
register when the L/U counter was not halted. Note that a word
write to certain L and H registers can be half successful and half
unsuccessful.
The most recent bus error from this SCT involved writing CTR
H, STATE H, MATCH H, or the Output register when the H
counter was not halted.
Chapter 24: LPC18xx State Configurable Timer (SCT)
Section
UM10430
© NXP B.V. 2011. All rights reserved.
24.6.3, the
606 of 1164
Reset
value
0
Reset
value
0
-
0
0