LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 261

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
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User manual
15.6.3 Masked I/O
15.6.4 GPIO Interrupts
If either or both of these conditions is (are) not met, “writing to the pin” has no effect.
There are seven ways to change GPIO output bits:
The state of a port’s output bits can be read from its SET register. Reading any of the
registers described in
alternate functions.
A port’s MASK register defines which of its pins should be accessible in its MPORT
register. Zeroes in MASK enable the corresponding pins to be read from and written to
MPORT. Ones in MASK force a pin to read as 0 and its output bit to be unaffected by
writes to MPORT. When a port’s MASK register contains all zeros, its PORT and MPORT
registers operate identically for reading and writing.
Users of previous NXP devices with similar GPIO blocks should be aware of an
incompatibility: on the LPC11A1x, writing to the SET, CLR, and NOT registers is not
affected by the MASK register. On previous devices these registers were masked.
Applications in which interrupts can result in Masked GPIO operation, or in task switching
among tasks that do Masked GPIO operation, must treat code that uses the Mask register
as a protected/restricted region. This can be done by interrupt disabling or by using a
semaphore.
The simpler way to protect a block of code that uses a MASK register is to disable
interrupts before setting the MASK register, and re-enable them after the last operation
that uses the MPORT or MASK register.
More efficiently, software can dedicate a semaphore to the MASK registers, and
set/capture the semaphore controlling exclusive use of the MASK registers before setting
the MASK registers, and release the semaphore after the last operation that uses the
MPORT or MASK registers.
Two separate GPIO interrupt facilities are provided. With pin interrupts, up to eight GPIO
pins can each have separately-vectored, edge- or level-sensitive interrupts.
2. the pin must be selected for output by a 1 in its port’s DIR register.
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Writing to a Byte Pin register loads the output bit from the least significant bit.
Writing to a Word Pin register loads the output bit with the OR of all of the bits written.
(This feature follows the definition of “truth” of a multi-bit value in programming
languages.)
Writing to a port’s PORT register loads the output bits of all the pins written to.
Writing to a port’s MPORT register loads the output bits of pins identified by zeros in
corresponding positions of the port’s MASK register.
Writing ones to a port’s SET register sets output bits.
Writing ones to a port’s CLR register clears output bits.
Writing ones to a port’s NOT register toggles/complements/inverts output bits.
All information provided in this document is subject to legal disclaimers.
15.6.1
Rev. 00.13 — 20 July 2011
returns the state of pins, regardless of their direction or
Chapter 15: LPC18xx GPIO
UM10430
© NXP B.V. 2011. All rights reserved.
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