LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 944

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 887. Interrupt Set-Enable Register 0 register (ISER0 - address 0xE000 E100) bit description
Table 888. Interrupt Clear-Enable Register 0 (ICER0 - address 0xE000 E180) bit description
<Document ID>
User manual
Bit
27
28
29
31:30 -
Bit
0
1
2
4:3
5
6
7
8
Symbol
ICE_DAC
ICE_ER
ICE_DMA
-
ICE_ETHERNET Ethernet interrupt disable.
ICE_SDIO
ICE_LCD
ICE_USB0
Symbol
ISE_I2S
ISE_AES
ISE_SPIFI
42.1.8.2 Interrupt Clear-Enable Register 0
The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the
enabled state of those interrupts. Enabling interrupts is done through the ISER0 register
(Section
Description
DAC interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Event router interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
DMA interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Reserved
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
SDIO interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
LCD interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
USB0 interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Description
IS2 interrupt enable.
Write: writing 0 has no effect, writing 1 enables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
AES interrupt enable.
Write: writing 0 has no effect, writing 1 enables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
SPIFI interrupt enable.
Write: writing 0 has no effect, writing 1 enables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Reserved.
42.1.8.1).
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
0
0
0
0
Reset
value
0
0
0
0