LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 99

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

10.1 How to read this chapter
10.2 Basic configuration
10.3 Features
10.4 General description
<Document ID>
User manual
Remark: This chapter applies to parts LPC1850_30_20_10 rev “A”.
Remark: The VADC is not available on parts LPC1850_30_10_10 rev “A”.
Ethernet, USB0, USB1, and LCD related clocks are not available on all packages. See
Table
The CCU1/2 are configured as follows:
Table 75.
The CCUs switch the clocks to individual peripherals on or off.
Each CGU base clock has several clock branches which can be turned on or off
independently by the Clock Control Units CCU1 or CCU2. The branch clocks are
distributed between CCU1 and CCU2.
Table 76.
CCU1
CCU2
Base clock
BASE_APB3_CLK CLK_APB3_BUS
•
•
•
•
•
UM10430
Chapter 10: LPC18xx Clock Control Unit (CCU)
Rev. 00.13 — 20 July 2011
See
Do not reset the CCUs during normal operation.
The output clock for the EMC clock divider
with bit 16 in the CREG6 register
Auto mode activates the AHB disable protocol before switching off the branch clock.
Wake-up mode allows to select clocks to run automatically after a wake-up event.
4.
Table 75
CCU clocking and power control
CCU1 branch clocks
Base clock
BASE_M3_CLK
BASE_M3_CLK
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Branch clock
CLK_APB3_I2C1
CLK_APB3_DAC
Rev. 00.13 — 20 July 2011
(Table
Branch clock
CLK_M3_BUS
CLK_M3_BUS
37).
Description
peripheral clock.
Clock to the DAC register interface.
APB3 bus clock.
Clock to the I2C1 register interface and I2C1
(Table
84) must be configured together
Maximum frequency
150 MHz
150 MHz
© NXP B.V. 2011. All rights reserved.
User manual
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