LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 772

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 714. Register overview: SSP0 (base address 0x4008 3000)
[1]
Table 715. Register overview: SSP1 (base address 0x400C 5000)
[1]
<Document ID>
User manual
Name
RIS
MIS
ICR
DMACR
Name
CR0
CR1
DR
SR
CPSR
IMSC
RIS
MIS
ICR
DMACR
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
34.6.1 SSPControl Register 0
Access Address
RO
RO
WO
R/W
Access Address
R/W
R/W
R/W
RO
R/W
R/W
RO
RO
R/W
R/W
This register controls the basic operation of the SSP controller.
offset
0x018
0x01C
0x020
0x024
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
Description
Raw Interrupt Status Register
Masked Interrupt Status Register
SSPICR Interrupt Clear Register
SSP0 DMA control register
Description
Control Register 0. Selects the serial clock rate, bus type, and data size. 0
Control Register 1. Selects master/slave and other modes.
Data Register. Writes fill the transmit FIFO, and reads empty the receive
FIFO.
Status Register
Clock Prescale Register
Interrupt Mask Set and Clear Register
Raw Interrupt Status Register
Masked Interrupt Status Register
SSPICR Interrupt Clear Register
SSP1 DMA control register
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 34: LPC18xx SSP0/1
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0x0000
0008
0
-
0
Reset
value
0
0
0x0000
0003
0
0
0x0000
0008
0
-
0
[1]
[1]