LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 553

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 462. LCD Control register (CTRL, address 0x4000 8018) bit description
Bits
7
8
9
10
11
13:12
15:14
16
31:17
Symbol
LCDDUAL
BGR
BEBO
BEPO
LCDPWR
LCDVCOMP
-
WATERMARK LCD DMA FIFO watermark level.
-
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Single or Dual LCD panel selection.
STN LCD interface is:
0 = single-panel.
1 = dual-panel.
Color format selection.
0 = RGB: normal output.
1 = BGR: red and blue swapped.
Big-endian Byte Order.
Controls byte ordering in memory:
0 = little-endian byte order.
1 = big-endian byte order.
Big-Endian Pixel Ordering.
Controls pixel ordering within a byte:
0 = little-endian ordering within a byte.
1 = big-endian pixel ordering within a byte.
The BEPO bit selects between little and big-endian pixel packing
for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp
pixel formats.
See Pixel serializer for more information on the data format.
LCD power enable.
0 = power not gated through to LCD panel and LCDV[23:0]
signals disabled, (held LOW).
1 = power gated through to LCD panel and LCDV[23:0] signals
enabled, (active).
See LCD power-up and power-down sequence for details on
LCD power sequencing.
LCD Vertical Compare Interrupt.
Generate VComp interrupt at:
00 = start of vertical synchronization.
01 = start of back porch.
10 = start of active video.
11 = start of front porch.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Controls when DMA requests are generated:
0 = An LCD DMA request is generated when either of the DMA
FIFOs have four or more empty locations.
1 = An LCD DMA request is generated when either of the DMA
FIFOs have eight or more empty locations.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
…continued
553 of 1164
Reset
value
0x0
0x0
0x0
0x0
0x0
0x0
-
0x0
-