LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 527

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
22.9 Ethernet descriptors (enhanced format)
<Document ID>
User manual
22.8.2.10 Error response to DMA
22.9.1 Transmit descriptor
the corresponding RI is enabled in DMA Interrupt Enable register
gets disabled before it runs out, when a frame is transferred to memory and the RI is set
because it is enabled for that descriptor.
For any data transfer initiated by a DMA channel, if the slave replies with an error
response, that DMA stops all operations and updates the error bits and the Fatal Bus
Error bit in the DMA Status register
operation only after soft resetting or hard resetting the core and re-initializing the DMA.
This DMA behavior is true for non-AHB interfaced DMAs that receive an error response.
The enhanced descriptor structure supports up to 8 DWORDS (32 bytes) and the IEEE
1588-2008 Advanced Timestamp feature or the AV feature. The features of the enhanced
descriptor structure are:
The description or bit-mapping alternate descriptor structure (in little-endian mode) is
given below.
The transmit descriptor structure is shown in
program the control bits TDES0[31:20] during descriptor initialization. When the DMA
updates the descriptor, it write backs all the control bits except the OWN bit (which it
clears) and updates the status bits[19:0]. The contents of the transmitter descriptor word 0
(TDES0) through word 3 (TDES3) are given in
With the advance timestamp support, the snapshot of the timestamp to be taken can be
enabled for a given frame by setting bit TTSE: Transmit Timestamp Enable. (bit-25 of
TDES0). When the descriptor is closed (i.e. when the OWN bit is cleared), the time-stamp
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Enhanced descriptor size can be 4 DWORDS (16 bytes) or 8 DWORDS (32 bytes)
depending on the setting of the ATDS bit in the DMA Bus Mode register
Support buffers of up to 8 KB (useful for Jumbo frames).
The transmit descriptor stores the timestamp in TDES6 and TDES7 when you select
the Advanced Timestamp.
This receive descriptor structure is also used for storing the extended status (RDES4)
and timestamp (RDES6 and RDES7) when advanced timestamp feature or IPC full
offload is selected.
When the enhanced descriptor mode is selected, and the Timestamp feature is
enabled, the software needs to allocate 32-bytes (8 DWORDS) of memory for every
descriptor. When Timestamping or Receive IPC FullOffload engine are not enabled,
the extended descriptors are not required and the SW can use alternate descriptors
with the default size of 16 bytes. The core also needs to be configured for this change
using the bit 7 (ATDS: Alternate Descriptor Size) of DMA Bus Mode register
(Table
When an enhanced descriptor is chosen without Timestamp or Full IPC Offload
feature, the descriptor size is always 4 DWORDs (DES0-DES3).
421).
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
(Table
427). That DMA controller can resume
Figure
Table 437
50. The application software must
Chapter 22: LPC18xx Ethernet
through
Table
(Table
UM10430
© NXP B.V. 2011. All rights reserved.
440, respectively.
429). This timer
(Table
527 of 1164
421).