LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 350

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
19.10 External static memory interface
<Document ID>
User manual
a. 32 bit wide memory bank interfaced to four 8 bit memory chips
b. 32 bit wide memory bank interfaced to two 16 bit memory chips
A[a_b:2]
19.10.1 32-bit wide memory bank connection
CS
OE
D[31:24]
BLS[3]
External memory interfacing depends on the bank width (32, 16 or 8 bit selected via MW
bits in corresponding StaticConfig register).
If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can be used
as non-address lines. If a memory bank is configured to 16 bits wide, A0 is not required.
However, 8 bit wide memory banks do require all address lines down to A0. Configuring
A1 and/or A0 line(s) to provide address or non-address function is accomplished using the
SYSCON registers.
Symbol "a_b" in the following figures refers to the highest order address line in the data
bus. Symbol "a_m" refers to the highest order address line of the memory chip used in the
external memory interface.
If the external memory is used as external boot memory for flashless devices, refer to
Section 3.2
2 is determined by the setting of the BOOT pins.
CE
OE
WE
IO[7:0]
A[a_m:0]
A[a_b:2]
WE
OE
CS
on how to connect the EMC. The memory bank width for memory banks 1 and
D[23:16]
All information provided in this document is subject to legal disclaimers.
D[31:16]
BLS[2]
BLS[3]
BLS[2]
Rev. 00.13 — 20 July 2011
CE
OE
WE
IO[7:0]
A[a_m:0]
CE
OE
WE
UB
LB
IO[15:0]
A[a_m:0]
Chapter 19: LPC18xx External Memory Controller (EMC)
D[15:8]
D[15:0]
BLS[1]
BLS[0]
BLS[1]
CE
OE
WE
UB
LB
IO[15:0]
A[a_m:0]
CE
OE
WE
IO[7:0]
A[a_m:0]
BLS[0]
D[7:0]
UM10430
© NXP B.V. 2011. All rights reserved.
CE
OE
WE
IO[7:0]
A[a_m:0]
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