LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 51
LPC1837FET256,551
Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1837FET256,551
Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Details
Other names
935293795551
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User manual
6.6.7 Clear status register
Table 25.
Table 26.
Bit
16
18:17
19
31:20
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Symbol
TIM14_EN
-
RESET_EN
-
Symbol
WAKEUP0_CLRST
WAKEUP1_CLRST
WAKEUP2_CLRST
WAKEUP3_CLRST
ATIMER_CLRST
RTC_CLRST
BOD_CLRST
WWDT_CLRST
ETH_CLRST
USB0_CLRST
USB1_CLRST
-
CAN_CLRST
TIM2_CLRST
TIM6_CLRST
QEI_CLRST
Event enable register (ENABLE - address 0x4004 4FE4) bit description
Interrupt clear status register (CLR_STAT - address 0x4004 4FE8) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
A 1 in this bit shows that the TIM14 event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.
A 1 in this bit shows that the RESET event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.
Reserved.
Description
Writing a 1 to this bit clears the STATUS event bit 0 in
the STATUS register.
Writing a 1 to this bit clears the STATUS event bit 1 in
the STATUS register.
Writing a 1 to this bit clears the STATUS event bit 2 in
the STATUS register.
Writing a 1 to this bit clears the STATUS event bit 3 in
the STATUS register.
Writing a 1 to this bit clears the STATUS event bit 4 in
the STATUS register.
Writing a 1 to this bit clears the STATUS event bit 5 in
the STATUS register.
Writing a 1 to this bit clears the STATUS event bit 6 in
the STATUS register.
Writing a 1 to this bit clears the STATUS event bit 7 in
the STATUS register.
Writing a 1 to this bit clears the STATUS event bit 8 in
the STATUS register.
Writing a 1 to this bit clears the STATUS event bit 9 in
the STATUS register.
the STATUS register.
Reserved.
Writing a 1 to this bit clears the STATUS event bit 12 in
the STATUS register.
the STATUS register.
the STATUS register.
Writing a 1 to this bit clears the STATUS event bit 15 in
the STATUS register.
Writing a 1 to this bit clears the STATUS event bit 10 in
Writing a 1 to this bit clears the STATUS event bit 13 in
Writing a 1 to this bit clears the STATUS event bit 14 in
Chapter 6: LPC18xx Event router
UM10430
© NXP B.V. 2011. All rights reserved.
51 of 1164
Reset
value
0
-
0
-
Reset
value
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