LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 594

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 500. SCT configuration register (CONFIG - address 0x4000 0000) bit description
<Document ID>
User manual
Bit
6:3
7
8
16:9
31:17
Symbol
CLKSEL
NORELAODL_
NORELOADU
NORELOADH
INSYNCn
-
24.6.2 SCT control register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
CTRL_L (address 0x4000 4004) and CTRL_H (address 0x4000 4006). Both the L and H
registers can be read or written in a single 32-bit read or write operation, or they can be
read or written individually.
All bits in this register can be written to when the counter is stopped or halted. When the
counter is running, the only bits that can be written are STOP or HALT. (Other bits can be
written in a subsequent write after HALT is set to 1.)
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
-
-
-
A 1 in this bit prevents the higher match registers from being reloaded from their
Description
SCT clock select
Rising edges on input 0.
Falling edges on input 0.
Rising edges on input 1.
Falling edges on input 1.
Rising edges on input 2.
Falling edges on input 2.
Rising edges on input 3.
Falling edges on input 3.
Rising edges on input 4.
Falling edges on input 4.
Rising edges on input 5.
Falling edges on input 5.
Rising edges on input 6.
Falling edges on input 6.
Rising edges on input 7.
Falling edges on input 7.
A 1 in this bit prevents the lower match registers from being reloaded from their
respective reload registers. Software can write to set or clear this bit at any
time. This bit applies to both the higher and lower registers when the UNIFY bit
is set.
respective reload registers. Software can write to set or clear this bit at any
time. This bit is not used when the UNIFY bit is set.
Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A
1 in one of these bits subjects the corresponding input to synchronization to the
SCT clock, before it is used to create an event. If an input is synchronous to the
SCT clock, keep its bit 0 for faster response.
When the CKMODE field is 1x, the bit in this field, corresponding to the input
selected by the CKSEL field, is not used.
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 24: LPC18xx State Configurable Timer (SCT)
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
594 of 1164
Reset
value
0000
0
0
1
-