LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 466

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 389. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description
<Document ID>
User manual
Bit
7
8
9
11:10 LS
Symbol
SUSP
PR
HSP
…continued
Value Description
0
1
0
1
0
1
0x0
0x1
0x2
0x3
Suspend
High-speed status
J-state (USB_DP HIGH and USB_DM LOW)
Undefined
Together with the PE (Port enabled bit), this bit describes the port states,
see
PORTSC1
The host controller will unconditionally set this bit to zero when software
sets the Force Port Resume bit to zero. The host controller ignores a write
of zero to this bit.
If host software sets this bit to a one when the port is not enabled (i.e. Port
enabled bit is a zero) the results are undefined.
This bit is 0 if PP (Port Power bit) is 0.
Port not in suspend state
Port in suspend state
When in suspend state, downstream propagation of data is blocked on this
port, except for port reset. The blocking occurs at the end of the current
transaction if a transaction was in progress when this bit was written to 1.
In the suspend state, the port is sensitive to resume detection. Note that
the bit status does not change until the port is suspended and that there
may be a delay in suspending a port if there is a transaction currently in
progress on the USB.
Port reset
When software writes a one to this bit the bus-reset sequence as defined in
the USB Specification Revision 2.0 is started. This bit will automatically
change to zero after the reset sequence is complete. This behavior is
different from EHCI where the host controller driver is required to set this
bit to a zero after the reset duration is timed in the driver.
This bit is 0 if PP (Port Power bit) is 0.
Port is not in the reset state.
Port is in the reset state.
Host/device connected to the port is not in High-speed mode.
Host/device connected to the port is in High-speed mode.
Line status
These bits reflect the current logical levels of the USB_DP and USB_DM
signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10.
In host mode, the use of linestate by the host controller driver is not
necessary for this controller (unlike EHCI) because the controller hardware
manages the connection of LS and FS.
SE0 (USB_DP and USB_DM LOW)
K-state (USB_DP LOW and USB_DM HIGH)
Table 390 “Port states as described by the PE and SUSP bits in the
register”.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 21: LPC18xx USB1 Host/Device controller
UM10430
Reset
value
0
0
0
0x3
© NXP B.V. 2011. All rights reserved.
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Access
R/W
R/W
RO
RO