LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 745

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
33.5 Register description
<Document ID>
User manual
UART1 contains registers organized as shown in
(DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches.
Reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
Table 689: Register overview: UART1 (base address 0x4008 2000)
Name
RBR
THR
DLL
DLM
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
ACR
FDR
TER
RS485CTRL
All information provided in this document is subject to legal disclaimers.
Access Address
RO
WO
R/W
R/W
R/W
RO
WO
R/W
R/W
RO
RO
R/W
R/W
R/W
R/W
R/W
Rev. 00.13 — 20 July 2011
0x000
0x008
0x010
0x014
0x018
0x020
0x04C
offset
0x000
0x000
0x004
0x004
0x008
0x00C
0x01C
0x028
0x030
Description
Receiver Buffer Register. Contains the next
received character to be read. (DLAB=0)
Transmit Holding Register. The next character to
be transmitted is written here. (DLAB=0)
Divisor Latch LSB. Least significant byte of the
baud rate divisor value. The full divisor is used to
generate a baud rate from the fractional rate
divider. (DLAB=1)
Divisor Latch MSB. Most significant byte of the
baud rate divisor value. The full divisor is used to
generate a baud rate from the fractional rate
divider.(DLAB=1)
Interrupt Enable Register. Contains individual
interrupt enable bits for the 7 potential UART1
interrupts. (DLAB=0)
Interrupt ID Register. Identifies which interrupt(s)
are pending.
FIFO Control Register. Controls UART1 FIFO
usage and modes.
Line Control Register. Contains controls for
frame formatting and break generation.
Modem Control Register. Contains controls for
flow control handshaking and loopback mode.
Line Status Register. Contains flags for transmit
and receive status, including line errors.
Modem Status Register. Contains handshake
signal status flags.
Scratch Pad Register. 8-bit temporary storage for
software.
Auto-baud Control Register. Contains controls
for the auto-baud feature.
Fractional Divider Register. Generates a clock
input for the baud rate divider.
Transmit Enable Register. Turns off UART
transmitter for use with software flow control.
RS-485/EIA-485 Control. Contains controls to
configure various aspects of RS-485/EIA-485
modes.
Table
689. The Divisor Latch Access Bit
Chapter 33: LPC18xx UART1
UM10430
© NXP B.V. 2011. All rights reserved.
745 of 1164
Reset
value
NA
NA
0x01
0x00
0x00
0x01
0x00
0x00
0x00
0x60
0x00
0x00
0x00
0x10
0x80
0x00