LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 322

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

19.1 How to read this chapter
19.2 Basic configuration
19.3 Features
<Document ID>
User manual
The EMC is available on all LPC18xx parts.
The reset value of the EMCSTATICWAITRD0 register varies with the part revision:
For LPC1850/30/20/10 Rev ‘A’ only: The EMC supports a CCLK clock which is half of the
frequency of the BASE_M3_CLK. The EMC divided clock must be configured for
half-frequency clock operation in both the CREG6 register
CLK_EMCDIV_CFG register
The External Memory Controller is configured as follows:
Table 262. EMC clocking and power control
EMC
registers
EMC CCLK
•
•
•
•
•
•
•
•
•
•
UM10430
Chapter 19: LPC18xx External Memory Controller (EMC)
Rev. 00.13 — 20 July 2011
LPC1850/30/20/10 Rev ‘A’: Reset value of the EMCSTATICWAITRD0 register is
0x0000 000E.
LPC1850/30/20/10 Rev ‘-’: Reset value of the EMCSTATICWAITRD0 register is
0x0000 0007.
See
If the EMC CCLK is using the divided clock, the CLK_M3_EMC_DIV branch clock
must be configured for half-frequency clock operation in both the CREG6 register
(Table
The EMC is reset by the EMC_RST (reset # 21).
Delay value for address, data, and command lines can be programmed through
registers in the SCU block. (See
Dynamic chip selects each support up to 256 MB of data.
Dynamic memory interface support including Single Data Rate SDRAM.
Asynchronous static memory device support including RAM, ROM, and NOR Flash,
with or without asynchronous page mode.
Low transaction latency.
Table 262
37) and the CCU1 CLK_EMCDIV_CFG register
Base clock
BASE_M3_CLK
BASE_M3_CLK
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Rev. 00.13 — 20 July 2011
(Table
Branch clock
CLK_M3_EMC
CLK_M3_EMC_DIV
84).
Section 19.4.4
Maximum
frequency
120 MHz
120 MHz
to
Section
(Table
(Table
19.4.12.)
37) and the CCU1
Notes
-
This is the CCLK clock for
the EMC timing.
84).
© NXP B.V. 2011. All rights reserved.
User manual
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