LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 325

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
19.6 Pin description
19.7 Register description
Table 265. Register overview: External memory controller (base address 0x4000 5000)
<Document ID>
User manual
Name
CONTROL
STATUS
CONFIG
-
DYNAMICCONTROL
DYNAMICREFRESH
DYNAMICREADCONFIG
-
DYNAMICRP
DYNAMICRAS
DYNAMICSREX
DYNAMICAPR
DYNAMICDAL
DYNAMICWR
DYNAMICRC
DYNAMICRFC
Table 264. EMC pin description
This chapter describes the EMC registers and provides details required when
programming the microcontroller. The EMC registers are shown in
Reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
Function pinned out
EMC_A[22:0]
EMC_D[31:0]
EMC_BLS[3:0]
EMC_CS[3:0]
EMC_OE
EMC_WE
EMC_CKEOUT[3:0]
EMC_CLK[3:0]
EMC_DQMOUT[3:0]
EMC_DYCS[3:0]
EMC_CAS
EMC_RAS
Access Address
R/W
RO
R/W
-
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
offset
0x000
0x004
0x008
0x00C -
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
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Configures dynamic memory refresh operation.
Configures the dynamic memory read strategy.
Selects the last-data-out to active command time.
Description
Controls operation of the memory controller.
Provides EMC status information.
Configures operation of the memory controller.
Reserved.
Controls dynamic memory operation.
Reserved.
Selects the precharge command period.
Selects the active to precharge command period.
Selects the self-refresh exit time.
Selects the data-in to active command time.
Selects the write recovery time.
Selects the active to active command period.
Selects the auto-refresh period.
Rev. 00.13 — 20 July 2011
Direction
O
I/O
O
O
O
O
O
O
O
O
O
O
Chapter 19: LPC18xx External Memory Controller (EMC)
Description
Address bus
Data bus
Byte lane select
Static RAM memory bank select
Output enable
Write enable
SDRAM clock enable signals
SDRAM clock signals
Data mask output to SDRAM memory banks
SDRAM memory bank select
Column address strobe
Row address strobe
Table
UM10430
© NXP B.V. 2011. All rights reserved.
265.
Reset value
0x0000
0003
0x0000 0005
0x0
-
0x0000 0006
0x0
0x0
-
0x0000 000F
0x0000 000F
0x0000 000F
0x0000 000F
0x0000 000F
0x0000 000F
0x0000 001F
0x0000 001F
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