LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 56

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
7.4.2 CREG0 control register
7.4.3 Power mode control register
Table 31.
For details on power mode selection, see
Bit
0
1
2
3
4
5
7:6
9:8
11:10
31:12
Symbol
EN1KHZ
EN32KHZ
RESET32KHZ
32KHZPD
-
USB0PHY
ALARMCTRL
BODLVL1
BODLVL2
-
CREG0 register (CREG0, address 0x4004 3004) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value
0
1
0
1
0
1
0
1
0
1
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
Description
Enable 1 kHz output.
1 kHz output disabled.
1 kHz output enabled.
Enable 32 kHz output
32 kHz output disabled.
32 kHz output enabled.
32 kHz oscillator reset
<tbd>
<tbd>
32 kHz power control.
32 kHz oscillator powered.
32 kHz oscillator powered-down.
Reserved
USB0 PHY power control.
USB0 PHY powered.
USB0 PHY powered down.
RTC_ALARM pin output control
RTC alarm.
Event router event.
Event router or <tbd>.
Inactive.
BOD trip level to generate an interrupt.
2.75 V
2.85 V
2.95 V
3.05 V
BOD trip level to generate a reset.
1.70 V
1.80 V
1.90 V
2.00 V
Reserved
Chapter 7: LPC18xx Configuration Registers (CREG)
Section
8.2.
UM10430
Reset
value
0
0
1
1
-
<tbd>
<tbd>
11
11
-
© NXP B.V. 2011. All rights reserved.
Access
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
-
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