LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 797

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 741. I2S Receive Clock Rate register (RXBITRATE - address 0x400A 202C (I2S0) and 0x400A 302C (I2S1)) bit
Table 742. I2S Transmit Mode Control register (TXMODE - address 0x400A 2030 (I2S0) and 0x400A 3030 (I2S1)) bit
Table 743. I2S Receive Mode Control register (RXMODE - address 0x400A 2034 (I2S0) and 0x400A 3034 (I2S1)) bit
<Document ID>
User manual
Bit
5:0
31:6
Bit
1:0
2
3
31:4
Bit
1:0
Symbol
TXCLKSEL
TX4PIN
TXMCENA
-
Symbol
RXCLKSEL
Symbol
RX_BITR
ATE
-
description
description
description
35.6.12 I2S Receive Clock Bit Rate register
35.6.13 I2S Transmit Mode Control register
35.6.14 I2S Receive Mode Control register
Description
I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit
clock.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Value Description
0x0
0x1
0x2
0x3
Value Description
0x0
0x1
0x2
0x3
The bit rate for the I2S receiver is determined by the value of the RXBITRATE register.
The value depends on the audio sample rate, as well as the data size and format used.
The calculation is the same as for RXBITRATE.
The Transmit Mode Control register contains additional controls for transmit clock source,
enabling the 4-pin mode, and how MCLK is used. See
useful mode combinations.
The Receive Mode Control register contains additional controls for receive clock source,
enabling the 4-pin mode, and how MCLK is used. See
useful mode combinations.
Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1,
Clock source selection for the transmit bit clock divider.
Select the TX fractional rate divider clock output as the source
Reserved
Select the RX_MCLK signal as the TX_MCLK clock source
Reserved
Transmit 4-pin mode selection. When 1, enables 4-pin mode.
output of TX_MCLK is enabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Clock source selection for the receive bit clock divider.
Select the RX fractional rate divider clock output as the source
Reserved
Select the TX_MCLK signal as the RX_MCLK clock source
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 35: LPC18xx I2S interface
Section 35.7.2
Section 35.7.2
UM10430
for a summary of
for a summary of
© NXP B.V. 2011. All rights reserved.
797 of 1164
Reset
value
0
0
0
NA
Reset
value
0
Reset
value
0
-