LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 734

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
32.5.17 UART1 RS485 Delay value register
32.5.18 UART Synchronous mode control register
The
received address value to. During automatic address detection, this value is used to
accept or reject serial input data.
The user may program the 8-bit RS485DLY register with a delay between the last stop bit
leaving the TXFIFO and the de-assertion of the DIR pin. This delay time is in periods of
the baud clock. Any delay time from 0 to 255 bit times may be programmed.
Table 684. UART RS485 Delay value register (RS485DLY - addresses 0x4008 1054 (UART0),
SYNCCTRL register is a Read/write register that controls the synchronous mode. The
synchronous mode control module generates or receives the synchronous clock with the
serial input/ output data and distributes the edge detect samples to the transmit and
receive shift registers.
Table 685. UART Synchronous mode control registers (SYNCCTRL - address addresses
Bit
7:0
31:8
Bit
0
1
2
3
4
ADRMATCH
Symbol
DLY
-
Symbol
SYNC
CSRC
FES
TSBYPASS
CSCEN
0x400C 1054 (UART2), 0x400C 2054 (UART3)) bit description
0x4008 1058 (UART0), 0x400C 1058 (UART2), 0x400C 2058 (UART3)) bit
description
All information provided in this document is subject to legal disclaimers.
bit field contains the slave address match value that is used to compare a
Description
Contains the direction control delay value. This register works in
conjunction with an 8-bit counter.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
Value
0
1
0
1
0
1
0
1
0
1
Description
Enables synchronous mode.
Disabled
Enabled
Clock source select.
Synchronous slave mode (SCLK in)
Synchronous master mode (SCLK out)
Falling edge sampling.
RxD is sampled on the rising edge of SCLK
RxD is sampled on the falling edge of SCLK
Transmit synchronization register bypass.
<tbd>
<tbd>
Continuous master clock enable (used only when
CSRC is 1)
SCLK cycles only when characters are being sent on
TxD
SCLK runs continuously (characters can be received on
RxD independently from transmission on TxD)
Chapter 32: LPC18xx USART0_2_3
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x00
NA
734 of 1164
Reset
value
0
0
0
0
0