LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 692

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
30.4 Applications
30.5 Description
<Document ID>
User manual
30.5.1 WWDT behavior in debug mode
The purpose of the Watchdog Timer is to reset the microcontroller within a reasonable
amount of time if it enters an erroneous state. When enabled, a watchdog event will be
generated if the user program fails to feed (or reload) the Watchdog within a
predetermined amount of time. The Watchdog event will cause a chip reset if configured
to do so.
When a watchdog window is programmed, an early watchdog feed is also treated as a
watchdog event. This allows preventing situations where a system failure may still feed
the watchdog. For example, application code could be stuck in an interrupt service that
contains a watchdog feed. Setting the window such that this would result in an early feed
will generate a watchdog event, allowing for system recovery.
The Watchdog consists of a fixed divide by 4 pre-scaler and a 24-bit counter which
decrements on every clock cycle. The minimum value from which the counter decrements
is 0xFF. Setting a value lower than 0xFF causes 0xFF to be loaded in the counter. Hence
the minimum Watchdog interval is (T
interval is (T
in the following manner:
When the Watchdog Timer is configured so that a watchdog event will cause a reset and
the counter reaches zero, the CPU will be reset, loading the stack pointer and program
counter from the vector table as in the case of external reset. The Watchdog time-out flag
(WDTOF) can be examined to determine if the Watchdog has caused the reset condition.
The WDTOF flag must be cleared by software.
When the Watchdog Timer is configured to generate a warning interrupt, the interrupt will
occur when the counter matches the compare value defined by the WARNINT register.
If code execution is halted in Debug mode, the WWDT stops counting until code execution
resumes.
•
•
•
•
•
•
Set the Watchdog time-out value in TC register.
Setup the Watchdog timer operating mode in MOD register.
Set a value for the watchdog window time in WINDOW register if windowed operation
is required.
Set a compare value for the watchdog warning interrupt in the WARNINT register if a
warning interrupt is required.
Enable the Watchdog by writing 0xAA followed by 0x55 to the FEED register.
The Watchdog must be fed again before the Watchdog counter reaches zero in order
to prevent a watchdog event. If a window value is programmed, the feed must also
occur after the watchdog counter passes that value.
WDCLK
All information provided in this document is subject to legal disclaimers.
 2
24
Rev. 00.13 — 20 July 2011
 4) in multiples of (T
Chapter 30: LPC18xx Windowed Watchdog timer (WWDT)
WDCLK
 256  4) and the maximum Watchdog
WDCLK
 4). The Watchdog should be used
UM10430
© NXP B.V. 2011. All rights reserved.
692 of 1164