LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 609

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 524. SCT event control register 0 to 15 (EVCTRL - address 0x4000 0304 (EVCTRL0) to 0x4000 037C
<Document ID>
User manual
Bit
3:0
4
5
9:6
11:10 IOCOND
13:12 COMBMODE
Symbol
MATCHSEL
HEVENT
OUTSEL
IOSEL
(EVCTRL15)) bit description
Value Description
-
0
1
0
1
-
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
When the UNIFY bit is 0, each event is associated with a particular counter by the
HEVENT bit in its event control register. An event can not occur when its related counter is
halted nor when the current state is not enabled to cause the event as specified in its
event mask register. Note that an event is permanently disabled when its event state
mask register contains all 0s.
An enabled event can be programmed to occur based on a selected input or output edge
or level and/or based on its counter value matching a selected match register.
Each event can modify its counter’s STATE value. If more than one event associated with
the same counter occurs in a given clock cycle, only the state change specified for the
highest-numbered event among them takes place. Other actions dictated by any
simultaneously occurring events will all take place.
Selects the Match register associated with this event (if any). A match can occur only
when the counter selected by the HEVENT bit is running.
Select L/H counter. Do not set this bit if UNIFY = 1.
Selects the L state and the L match register selected by MATCHSEL.
Selects the H state and the H match register selected by MATCHSEL.
Input/output select
Selects the output selected by IOSEL.
Selects the input selected by IOSEL.
Selects the input or output signal associated with this event (if any). If CKMODE is 1x,
the clock input is an implicit ingredient of every event, and should not be selected in
this register.
Selects the I/O condition for event n. (Note that the detection of edges on outputs will
lag the conditions that switch the outputs by one SCT clock). An input must have a
minimum pulse width of at least one SCT clock period in order to guarantee proper
edge/state detection.
Rise
Fall
HIGH
Selects how the specified match and I/O condition are used and combined.
OR. The event occurs when either the specified match or I/O condition occurs.
MATCH. Uses the specified match only.
IO. Uses the specified I/O condition only.
AND. The event occurs when the specified match and I/O condition occur
simultaneously.
LOW
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 24: LPC18xx State Configurable Timer (SCT)
UM10430
© NXP B.V. 2011. All rights reserved.
609 of 1164
Reset
value
0
0
0
0
0