LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 502

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 427. DMA Status register (DMA_STAT, address 0x4001 1014) bit description
<Document ID>
User manual
Bit
15
16
31:17
Symbol
AIE
NIS
-
22.6.23 DMA Operation mode register
Description
Abnormal interrupt summary
Abnormal Interrupt Summary bit value is the logical OR of the following when the
corresponding interrupt bits are enabled in the DMA_INT_EN register:
DMA_STAT register, bit 1: Transmit process stopped
DMA_STAT register, bit 3: Transmit jabber timeout
DMA_STAT register, bit 4: Receive overflow
DMA_STAT register, bit 5: Transmit underflow
DMA_STAT register, bit 7: Receiver buffer unavailable
DMA_STAT register, bit 8: Receive process stopped
DMA_STAT register, bit 9: Receive watchdog timeout
DMA_STAT register, bit 10: Early transmit interrupt
DMA_STAT register, bit 13: Fatal bus error
Only unmasked bits affect the Abnormal Interrupt Summary bit.
This is a sticky bit and must be cleared each time a corresponding bit that causes AIS
to be set is cleared.
Normal interrupt summary
Normal Interrupt Summary bit value is the logical OR of the following when the
corresponding interrupt bits are enabled in the DMA_INT_EN register:
DMA_STAT register, bit 0: Transmit interrupt
DMA_STAT register, bit 2: Transmit buffer unavailable
DMA_STAT register, bit 6: Receive interrupt
DMA_STAT register, bit 14: Early receive interrupt
Only unmasked bits affect the Normal Interrupt Summary bit.
This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a
corresponding bit that causes NIS to be set is cleared.
Reserved
The Operation Mode register establishes the Transmit and Receive operating modes and
commands. This register should be the last CSR to be written as part of DMA initialization.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
502 of 1164
Access
R/SS/
WC
R/SS/
WC
RO