LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 622

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
25.4 General description
25.5 Pin description
<Document ID>
User manual
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally-supplied clock, and can optionally generate interrupts or perform other actions
at specified timer values, based on four match registers. It also includes four capture
inputs to trap the timer value when an input signal transitions, optionally generating an
interrupt.
Remark: The capture inputs are shared between four SCT inputs and the timer inputs.
The timer match outputs are ORed with the SCT outputs (see
Table 531. Timer0/1/2/3 pin description
Function name
Timer0
CTIN_[2:0]
CTOUT_[3:0]
Timer1
CTIN_0
CTIN_3
CTIN_4
CTOUT_[7:4]
Timer2
CTIN_0
CTIN_1
CTIN_5
•
•
•
•
Counter or Timer operation
Up to four 32 bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
Four 32 bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set low on match.
– Set high on match.
– Toggle on match.
– Do nothing on match.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Direction
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Description
CAP0_[2:0]; capture inputs 2 to 0 of timer 0.
MAT0_[3:0]; match outputs 3:0 of timer 0 are ORed with
SCT outputs 3 to 0.
CAP1_0; capture input 0 of timer 1.
CAP1_1; capture input 1 of timer 1.
CAP1_2; capture input 2 of timer 1.
MAT1_[3:0]; match outputs 3:0 of timer 1 are ORed with
SCT outputs 7 to 4.
CAP2_0; capture input 0 of timer 2.
CAP2_1; capture input 1 of timer 2.
CAP2_2; capture input 2 of timer 2.
Chapter 25: LPC18xx Timer0/1/2/3
Figure
24).
UM10430
© NXP B.V. 2011. All rights reserved.
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