LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 102
LPC1837FET256,551
Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1837FET256,551
Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Details
Other names
935293795551
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10.5 Register description
Table 78.
<Document ID>
User manual
Name
PM
BASE_STAT
-
CLK_APB3_BUS_CFG
CLK_APB3_BUS_STAT
CLK_APB3_I2C1_CFG
CLK_APB3_I2C1_STAT
CLK_APB3_DAC_CFG
CLK_APB3_DAC_STAT
CLK_APB3_ADC0_CFG
CLK_APB3_ADC0_STAT
CLK_APB3_ADC1_CFG
CLK_APB3_ADC1_STAT
CLK_APB3_CAN0_CFG
CLK_APB3_CAN0_STAT
-
CLK_APB1_BUS_CFG
CLK_APB1_BUS_STAT
CLK_APB1_MOTOCONPWM_CFG
CLK_APB1_MOTOCONPWM_STAT
CLK_APB1_I2C0_CFG
CLK_APB1_I2C0_STAT
CLK_APB1_I2S_CFG
CLK_APB1_I2S_STAT
CLK_APB1_CAN1_CFG
CLK_APB1_CAN1_STAT
-
CLK_SPIFI_CFG
CLK_SPIFI_STAT
-
CLK_M3_BUS_CFG
CLK_M3_BUS_STAT
CLK_M3_SPIFI_CFG
CLK_M3_SPIFI_STAT
Register overview: CCU1 (base address 0x4005 1000)
Access
R/W
R
-
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
-
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
-
R/W
R
-
R/W
R
R/W
R
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
0x100
0x108
0x110
0x118
0x128
0x20C
0x210
0x218
0x40C
Address
offset
0x000
0x004
0x008 to
0x0FC
0x104
0x10C
0x114
0x11C
0x120
0x124
0x12C
0x130 to
0x1FC
0x200
0x204
0x208
0x214
0x21C
0x220
0x224
0x220 to
0x2FC
0x300
0x304
0x308 to
0x3FC
0x400
0x404
0x408
Description
CCU1 power mode register
CCU1 base clocks status register
Reserved
CLK_APB3_BUS clock configuration
register
CLK_APB3_BUS clock status register
CLK_APB3_I2C1 configuration register
CLK_APB3_I2C1v status register
CLK_APB3_DAC configuration register
CLK_APB3_DAC status register
CLK_APB3_ADC0 configuration register
CLK_APB3_ADC0 status register
CLK_APB3_ADC1 configuration register
CLK_APB3_ADC1 status register
CLK_APB3_CAN0 configuration register
CLK_APB3_CAN0 status register
Reserved
CLK_APB1_BUS configuration register
CLK_APB1_BUS status register
CLK_APB1_MOTOCON configuration
register
CLK_APB1_MOTOCON status register
CLK_APB1_I2C0 configuration register
CLK_APB1_I2C0 status register
CLK_APB1_I2S configuration register
CLK_APB1_I2S status register
CLK_APB3_CAN1 configuration register
CLK_APB3_CAN1 status register
Reserved
CLK_SPIFI configuration register
CLK_SPIFI status register
Reserved
CLK_M3_BUS configuration register
CLK_M3_BUS status register
CLK_M3_SPIFI configuration register
CLK_M3_SPIFI status register
Chapter 10: LPC18xx Clock Control Unit (CCU)
UM10430
© NXP B.V. 2011. All rights reserved.
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
Reset value
0x0000 0000
0x0000 0FFF
-
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
-
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
-
0x0000 0001
0x0000 0001
-
0x0000 0001
0x0000 0001
0x0000 0001
0x0000 0001
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