LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 72

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 48.
Name
IDIVA_CTRL
IDIVB_CTRL
IDIVC_CTRL
IDIVD_CTRL
IDIVE_CTRL
OUTCLK_0_CTRL
OUTCLK_1_CTRL
-
OUTCLK_3_CTRL
OUTCLK_4_CTRL
OUTCLK_5_CTRL
-
OUTCLK_7_CTRL
OUTCLK_8_CTRL
OUTCLK_9_CTRL
OUTCLK_10_CTRL
OUTCLK_11_CTRL
OUTCLK_12_CTRL
OUTCLK_13_CTRL
OUTCLK_14_CTRL
OUTCLK_15_CTRL
OUTCLK_16_CTRL
OUTCLK_17_CTRL
OUTCLK_18_CTRL
OUTCLK_19_CTRL
Register overview: CGU (base address 0x4005 0000)
All information provided in this document is subject to legal disclaimers.
Access Address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 00.13 — 20 July 2011
offset
0x048
0x04C
0x050
0x054
0x058
0x05C
0x060
0x064
0x068
0x06C
0x070
0x074
0x078
0x07C
0x080
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C
0x0A0
0x0A4
0x0A8
Chapter 9: LPC18xx Clock Generation Unit (CGU)
Description
Integer divider A control register
Integer divider B control register
Integer divider C control register
Integer divider D control register
Integer divider E control register
Output stage 0 control register for
base clock BASE_SAFE_CLK
Output stage 1 control register for
base clock BASE_USB0_CLK
Reserved
Output stage 3 control register for
base clock BASE_USB1_CLK
Output stage 4 control register for
base clock BASE_M3_CLK
Output stage 5 control register for
base clock BASE_SPIFI_CLK
Reserved
Output stage 7 control register for
base clock BASE_PHY_RX_CLK
Output stage 8 control register for
base clock BASE_PHY_TX_CLK
Output stage 9 control register for
base clock BASE_APB1_CLK
Output stage 10 control register for
base clock BASE_APB3_CLK
Output stage 11 control register for
base clock BASE_LCD_CLK
Output stage 11 control register for
base clock
BASE_ENET_CSR_CLK
Output stage 13 control register for
base clock BASE_SDIO_CLK
Output stage 14 control register for
base clock BASE_SSP0_CLK
Output stage 15 control register for
base clock BASE_SSP1_CLK
Output stage 16 control register for
base clock BASE_UART0_CLK
Output stage 17 control register for
base clock BASE_UART1_CLK
Output stage 18 control register for
base clock BASE_UART2_CLK
Output stage 19 control register for
base clock BASE_UART3_CLK
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0700 0000
-
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
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