LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 743
LPC1837FET256,551
Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1837FET256,551
Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Details
Other names
935293795551
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33.1 How to read this chapter
33.2 Basic configuration
33.3 Features
<Document ID>
User manual
The UART1 controller is available on all LPC18xx parts.
The UART1 is configured as follows:
Table 687. UART1 clocking and power control
UART1 clock to register interface
UART1 peripheral clock (PCLK)
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UM10430
Chapter 33: LPC18xx UART1
Rev. 00.13 — 20 July 2011
See
The UART1 is reset by the UART1_RST (reset #45).
The UART1 interrupt is connected to slot # 25 in the NVIC.
For connecting the UART1 receive and transmit lines to the GPDMA, use the
DMAMUX register in the CREG block (see
in the DMA Channel Configuration registers
Full modem control handshaking available.
Data sizes of 5, 6, 7, and 8 bits.
Parity generation and checking: odd, even mark, space or none.
One or two stop bits.
16 byte Receive and Transmit FIFOs.
Built-in baud rate generator, including a fractional rate divider for great versatility.
Supports DMA for both transmit and receive.
Auto-baud capability.
Break generation and detection.
Multiprocessor addressing mode.
RS-485 support.
Table 687
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Rev. 00.13 — 20 July 2011
Base clock
BASE_M3_CLK
BASE_UART1_CLK CLK_APB0_UART1 150 MHz
Table
(Section
35) and enable the GPDMA channel
16.6.20).
Branch clock
CLK_M3_UART0
© NXP B.V. 2011. All rights reserved.
User manual
Maximum
frequency
150 MHz
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