LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 109

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
10.5.4 CCU1/2 branch clock status registers
Table 85.
Like the Configuration Register, each generated output clock from the CCU has a status
register. When the configuration register of an output clock is written into, the value of the
actual hardware signals may not be updated immediately because of the Auto or Wake-up
mechanism. The Status Register shows the current value of these signals. All output clock
Status Registers follow the format as described in
Table 86.
Bit
0
1
2
31:3
Bit
0
1
2
31:3
Symbol
RUN
AUTO
WAKEUP
-
Symbol
RUN
AUTO
WAKEUP
-
CCU2 branch clock configuration register (CLK_XXX_CFG, addresses 0x4005
2100, 0x4005 2200,..., 0x4005 2800) bit description
CCU1 branch clock status register (CLK_XXX_STAT, addresses 0x4005 1104,
0x4005 110C,..., 0x4005 1A04) bit description
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Description
Run enable status
0 = clock is disabled.
1 = clock is enabled.
Auto (AHB disable mechanism) enable status
0 = Auto is disabled.
1 = Auto is enabled.
Wake-up mechanism enable status
0 = Wake-up is disabled.
1 = Wake-up is enabled.
Reserved
Description
Run enable
Clock is disabled.
Clock is enabled.
Auto (AHB disable mechanism) enable
Auto is disabled.
Auto is enabled.
Wake-up mechanism enable
Wake-up is disabled.
Wake-up is enabled.
Reserved
Chapter 10: LPC18xx Clock Control Unit (CCU)
Table 86
and
Table
UM10430
87.
Reset
value
1
0
0
-
© NXP B.V. 2011. All rights reserved.
Reset
value
1
0
0
-
109 of 1164
Access
R
R
R
-
Access
R/W
R/W
R/W
-