LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 428

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.10.11.1 Software link pointers
20.10.11.2 Building a transfer descriptor
20.10.11 Managing transfers with transfer descriptors
It is necessary for the DCD software to maintain head and tail pointers to the linked list of
dTDs for each respective queue head. This is necessary because the dQH only maintains
pointers to the current working dTD and the next dTD to be executed. The operations
described in next section for managing dTD will assume the DCD can use reference the
head and tail of the dTD linked list.
Remark: To conserve memory, the reserved fields at the end of the dQH can be used to
store the Head & Tail pointers but it still remains the responsibility of the DCD to maintain
the pointers.
Before a transfer can be executed from the linked list, a dTD must be built to describe the
transfer. Use the following procedure for building dTDs:
Allocate 8-DWord dTD block of memory aligned to 8-DWord boundaries. Example: bit
address 4:0 would be equal to “00000”.
Write the following fields:
1. Initialize first 7 DWords to 0.
2. Set the terminate bit to “1”.
3. Fill in total bytes with transfer size.
4. Set the interrupt on complete if desired.
5. Initialize the status field with the active bit set to “1” and all remaining status bits set to
6. Fill in buffer pointer page 0 and the current offset to point to the start of the data buffer.
7. Initialize buffer pointer page 1 through page 4 to be one greater than each of the
Fig 41. Software link pointers
“0”.
previous buffer pointer.
Head Pointer
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
completed dTDs
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Endpoint
QH
current
queued dTDs
next
UM10430
© NXP B.V. 2011. All rights reserved.
Tail Pointer
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