LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1129

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 334. USB Endpoint Flush register (ENDPTFLUSH -
Table 335. USB Endpoint Status register (ENDPTSTAT -
Table 336. USB Endpoint Complete register
Table 337. USB Endpoint 0 Control register (ENDPTCTRL0
Table 338. USB Endpoint 1 to 5 control registers
Table 339. Handling of directly connected full-speed and
Table 340. Split state machine properties . . . . . . . . . . . .403
Table 341. Endpoint capabilities and characteristics . . . .407
Table 342. Current dTD pointer . . . . . . . . . . . . . . . . . . .409
Table 343. Set-up buffer . . . . . . . . . . . . . . . . . . . . . . . . .409
Table 344. Next dTD pointer . . . . . . . . . . . . . . . . . . . . . .409
Table 345. dTD token . . . . . . . . . . . . . . . . . . . . . . . . . .410
Table 346. dTD buffer page pointer list . . . . . . . . . . . . . . 411
Table 347. Device controller endpoint initialization . . . . .417
Table 348. Device controller stall response matrix . . . . .418
Table 349. Variable length transfer protocol example (ZLT =
Table 350. Variable length transfer protocol example (ZLT =
Table 351. Interrupt/bulk endpoint bus response matrix .421
Table 352. Control endpoint bus response matrix . . . . . .424
Table 353. Isochronous endpoint bus response matrix . .426
Table 354. Device error matrix. . . . . . . . . . . . . . . . . . . . .431
Table 355. High-frequency interrupt events. . . . . . . . . . .431
Table 356. Low-frequency interrupt events . . . . . . . . . . .431
Table 357. Error interrupt events . . . . . . . . . . . . . . . . . . .432
Table 358. USB1 clocking and power control . . . . . . . . .437
Table 359. USB1 pin description . . . . . . . . . . . . . . . . . . .438
Table 360. Register access abbreviations . . . . . . . . . . . .439
Table 361. Register overview: USB1 host/device controller
Table 362. CAPLENGTH register (CAPLENGTH - address
Table 363. HCSPARAMS register (HCSPARAMS - address
Table 364. HCCPARAMS register (HCCPARAMS - address
Table 365. DCIVERSION register (DCIVERSION - address
Table 366. DCCPARAMS (address 0x4000 7124) . . . . .442
Table 367. USB Command register in device mode
Table 368. USB Command register in host mode
Table 369. Frame list size values . . . . . . . . . . . . . . . . . .446
Table 370. USB Status register in device mode (USBSTS_D
<Document ID>
User manual
address 0x4000 61B4) bit description . . . . . .392
address 0x4000 61B8) bit description . . . . . .393
(ENDPTCOMPLETE - address 0x4000 61BC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .394
- address 0x4000 61C0) bit description . . . .394
(ENDPTCTRL - address 0x4000 61C4
(ENDPTCTRL1) to 0x4000 61D4
(ENDPTCTRL5)) bit description . . . . . . . . . .395
low-speed devices . . . . . . . . . . . . . . . . . . . . .401
0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
(register base address 0x4000 7000) . . . . . .439
0x4000 7100) bit description . . . . . . . . . . . . .440
0x4000 7104) bit description
0x4000 7108) bit description . . . . . . . . . . . . .442
0x4000 7120) bit description . . . . . . . . . . . . .442
(USBCMD_D - address 0x4000 7140) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .443
(USBCMD_H - address 0x4000 7140) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .444
- address 0x4000 7144) register bit description .
. . . . . . . . . . . .441
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 371. USB Status register in host mode (USBSTS_H -
Table 372. USB Interrupt register in device mode
Table 373. USB Interrupt register in host mode (USBINTR_H
Table 374. USB frame index register in device mode
Table 375. USB frame index register in host mode
Table 376. Number of bits used for the frame list index . 453
Table 377. USB Device Address register in device mode
Table 378. USB Periodic List Base register in host mode
Table 379. USB Endpoint List Address register in device
Table 380. USB Asynchronous List Address register in host
Table 381. USB TT Control register in host mode (TTCTRL -
Table 382. USB burst size register in device/host mode
Table 383. USB Transfer buffer Fill Tuning register in host
Table 384. USB ULPI viewport register (ULPIVIEWPORT -
Table 385. USB BINTERVAL register (BINTERVAL - address
Table 386. USB endpoint NAK register in device mode
Table 387. USB Endpoint NAK Enable register in device
Table 388. Port Status and Control register in device mode
Table 389. Port Status and Control register in host mode
Table 390. Port states as described by the PE and SUSP bits
Table 391. USB Mode register in device mode
447
address 0x4000 7144) register bit description
449
(USBINTR_D - address 0x4000 7148) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 451
- address 0x4000 7148) bit description . . . . 452
(FRINDEX_D - address 0x4000 714C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
(FRINDEX_H - address 0x4000 714C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
(DEVICEADDR - address 0x4000 7154) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
(PERIODICLISTBASE - address 0x4000 7154) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
mode (ENDPOINTLISTADDR - address 0x4000
7158) bit description . . . . . . . . . . . . . . . . . . . 455
mode (ASYNCLISTADDR- address 0x4000 7158)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 455
address 0x4000 715C) bit description . . . . . 456
(BURSTSIZE - address 0x4000 7160) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
mode (TXFILLTUNING - address 0x4000 7164)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 457
address 0x4000 7170) bit description . . . . . 458
0x4000 7174) bit description in device/host mode
459
(ENDPTNAK - address 0x4000 7178) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
mode (ENDPTNAKEN - address 0x4000 717C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 461
(PORTSC1_D - address 0x4000 7184) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 461
(PORTSC1_H - address 0x4000 7184) bit
description
in the PORTSC1 register . . . . . . . . . . . . . . . . 469
(USBMODE_D - address 0x4000 71A8) bit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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