LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 401

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.8.1.2 Operational registers
20.8.1.3 Discovery
20.8.1.4 Data structures
The following items have been added to the operational registers to support the
embedded TT:
In a standard EHCI controller design, the EHCI host controller driver detects a Full speed
(FS) or Low speed (LS) device by noting if the port enable bit is set after the port reset
operation. The port enable will only be set in a standard EHCI controller implementation
after the port reset operation and when the host and device negotiate a High-Speed
connection (i.e. Chirp completes successfully). Since this controller has an embedded
Transaction Translator, the port enable will always be set after the port reset operation
regardless of the result of the host device chirp result and the resulting port speed will be
indicated by the PSPD field in PORTSC1 (see
Table 339. Handling of directly connected full-speed and low-speed devices
The same data structures used for FS/LS transactions though a HS hub are also used for
transactions through the Root Hub with sm embedded Transaction Translator. Here it is
demonstrated how the Hub Address and Endpoint Speed fields should be set for directly
attached FS/LS devices and hubs:
Standard EHCI model
After the port enable bit is set following a
connection and reset sequence, the device/hub
is assumed to be HS.
FS and LS devices are assumed to be
downstream from a HS hub thus, all port-level
control is performed through the Hub Class to
the nearest Hub.
FS and LS devices are assumed to be
downstream from a HS hub with HubAddr=X,
where HubAddr > 0 and HubAddr is the address
of the Hub where the bus transitions from HS to
FS/LS (i.e. Split target hub).
1. QH (for direct attach FS/LS) – Async. (Bulk/Control Endpoints) Periodic (Interrupt)
•
•
New register TTCTRL (see
Two-bit Port Speed (PSPD) bits added to the PORTSC1 register (see
Section
– Hub Address = TTHA (default TTHA = 0)
– Transactions to direct attached device/hub: QH.EPS = Port Speed
– Transactions to a device downstream from direct attached FS hub: QH.EPS =
Downstream Device Speed
20.6.15).
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Section
20.6.9).
EHCI with embedded Transaction Translator
After the port enable bit is set following a
connection and reset sequence, the device/hub
speed is noted from PORTSC1.
FS and LS device can be either downstream
from a HS hub or directly attached. When the
FS/LS device is downstream from a HS hub,
then port-level control is done using the Hub
Class through the nearest Hub. When a FS/LS
device is directly attached, then port-level
control is accomplished using PORTSC1.
FS and LS device can be either downstream
from a HS hub with HubAddr = X [HubAddr > 0]
or directly attached, where HubAddr = TTHA
(TTHA is programmable and defaults to 0) and
HubAddr is the address of the Root Hub where
the bus transitions from HS to FS/LS (i.e. Split
target hub is the root hub).
Section
20.6.15).
UM10430
© NXP B.V. 2011. All rights reserved.
401 of 1164