LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 412

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
20.10 Device operational model
<Document ID>
User manual
20.10.1 Device controller initialization
In this case three packets are sent: Data2 (8 bytes), Data1 (7 bytes), Data0 (0 bytes).
Example 2
MULT = 3; Max_packet_size = 8; Total_bytes = 15; MultO = 2
In this case two packets are sent: Data1 (8 bytes), Data0 (7 bytes).
To optimize efficiency for IN transfers, software should compute MultO = greatest integer
of (Total_bytes/Max_packet_size). If Total_bytes = 0, then MultO should be 1.
The function of the device operation is to transfer a request in the memory image to and
from the Universal Serial Bus. Using a set of linked list transfer descriptors, pointed to by
a queue head, the device controller will perform the data transfers. The following sections
explain the use of the device controller from the device controller driver (DCD)
point-of-view and further describe how specific USB bus events relate to status changes
in the device controller programmer's interface.
After hardware reset, the device is disabled until the Run/Stop bit is set to a ‘1’. In the
disabled state, the pull-up on the USB_DM is not active which prevents an attach event
from occurring. At a minimum, it is necessary to have the queue heads setup for endpoint
zero before the device attach occurs. Shortly after the device is enabled, a USB reset will
occur followed by setup packet arriving at endpoint 0. A Queue head must be prepared so
that the device controller can store the incoming setup packet.
In order to initialize a device, the software should perform the following steps:
1. Set Controller Mode in the USBMODE register to device mode.
2. Allocate and Initialize device queue heads in system memory (see
3. Configure ENDPOINTLISTADDR Pointer (see
4. Enable the microprocessor interrupt associated with the USB-HS core.
5. Set Run/Stop bit to Run Mode.
Remark: Transitioning from host mode to device mode requires a device controller
reset before modifying USBMODE.
Minimum: Initialize device queue heads 0 Tx & 0 Rx.
Remark: All device queue heads associated with control endpoints must be initialized
before the control endpoint is enabled. Non-Control device queue heads must be
initialized before the endpoint is used and not necessarily before the endpoint is
enabled.
Recommended: enable all device interrupts including: USBINT, USBERRINT, Port
Change Detect, USB Reset Received, DCSuspend (see
After the Run bit is set, a device reset will occur. The DCD must monitor the reset
event and adjust the software state as described in the Bus Reset section of the
following Port State and Control section below.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Section
20.6.8).
Table
311).
UM10430
Section
© NXP B.V. 2011. All rights reserved.
20.9).
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