LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 437

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

21.1 How to read this chapter
21.2 Basic configuration
21.3 Features
<Document ID>
User manual
21.2.1 Full-speed mode without external PHY
21.2.2 High-speed mode with ULPI interface
The USB1 Host/Device controller is available on parts LPC1850 and LPC1830.
The USB1 controller is configured as follows:
Table 358. USB1 clocking and power control
In Full-speed mode, use CLK_USB1 to generate a clock for the USB1 interface.
In High-speed mode, the external PHY generates the clock for the USB1 interface, and
the USB1_ULPI_CLK must be enabled on pins PC_0 or P8_8 through their respective pin
configuration registers in the system configuration block. The USB1 branch clock
CLK_USB1 must be disabled.
USB1 clock
USB1 register
interface clock
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UM10430
Chapter 21: LPC18xx USB1 Host/Device controller
Rev. 00.13 — 20 July 2011
See
The USB1 is reset by a USB1_RST (reset # 18).
The USB1 OTG interrupt is connected to interrupt slot # 9 in the NVIC. The USB
wake-up interrupt is connected to slot # 10 in the event router.
In the SFSUSB register, the USB_ESEA bit must be set to 1 for the USB1 to operate
(see
Complies with Universal Serial Bus specification 2.0.
Complies with Enhanced Host Controller Interface Specification.
Supports auto USB 2.0 mode discovery.
Supports all high-speed USB-compliant peripherals if connected to external ULPI
PHY.
Table 358
Table
204).
All information provided in this document is subject to legal disclaimers.
Base clock
BASE_USB1_CLK CLK_USB1
BASE_M3_CLK
for clocking and power control.
Rev. 00.13 — 20 July 2011
Branch clock
CLK_M3_USB1 150 MHz
Maximum
frequency
150 MHz
Notes
Uses PLL1 only. CLK_USB1
must be 60 MHz when the
USB1 is operated at
low-speed and full-speed
modes. In high-speed mode,
the clock is provided by the
ULPI PHY.
© NXP B.V. 2011. All rights reserved.
User manual
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