LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 315

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 248. Transferred CIU Card Byte Count Register (TCBCNT, address 0x4000 405C) bit description
<Document ID>
User manual
Bit
31:0
Symbol
TRANS_CARD_BYTE
_COUNT
18.6.21 Card Detect Register (CDETECT)
18.6.22 Write Protect Register (WRTPRT)
18.6.23 General Purpose Input/Output Register (GPIO)
18.6.24 Transferred CIU Card Byte Count Register (TCBCNT)
Table 245. Card Detect Register (CDETECT, address 0x4000 4050) bit description
Table 246. Write Protect Register (WRTPRT, address 0x4000 4054) bit description
Table 247. General Purpose Input/Output Register (GPIO, address 0x4000 4058) bit
Bit
29:0
31:30
Bit
29:0
31:30
Bit
7:0
23:8
31:24
Description
Number of bytes transferred by CIU unit to card. In 32-bit or 64-bit AMBA
data-bus-width modes, register should be accessed in full to avoid
read-coherency problems. In 16-bit AMBA data-bus-width mode, internal 16-bit
coherency register is implemented. User should first read lower 16 bits and then
higher 16 bits. When reading lower 16 bits, higher 16 bits of counter are stored in
temporary register. When higher 16 bits are read, data from temporary register is
supplied. Both TCBCNT and TBBCNT share same coherency register.
When AREA_OPTIMIZED parameter is 1, register should be read only after data
transfer completes; during data transfer, register returns 0.
Symbol
CARD_DETECT_N
-
Symbol
GPI
GPO
-
Symbol
WRITE_PROTECT
-
description
All information provided in this document is subject to legal disclaimers.
Description
Value on gpi input ports; this portion of register is read-only. Valid
only when AREA_OPTIMIZED parameter is 0.
Value needed to be driven to gpo pins; this portion of register is
read/write. Valid only when AREA_OPTIMIZED parameter is 0.
Reserved
Rev. 00.13 — 20 July 2011
Description
Value on card_write_prt input ports (1 bit per card). 1
represents write protection. Only NUM_CARDS
number of bits are implemented.
Reserved
Description
Value on card_detect_n input ports (1 bit per card);
read-only bits. 0 represents presence of card. Only
NUM_CARDS number of bits are implemented.
Reserved
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
Reset
value
0
Reset
value
0
Reset
value