LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 771

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
34.5 Pin description
Table 713. SSP pin description
34.6 Register description
Table 714. Register overview: SSP0 (base address 0x4008 3000)
<Document ID>
User manual
Pin
Name
SCK0/1
SSEL0/1 I/O
MISO0/1 I/O
MOSI0/1 I/O
Name
CR0
CR1
DR
SR
CPSR
IMSC
Direction
I/O
Access Address
R/W
R/W
R/W
RO
R/W
R/W
Interface pin
name/function
SPI
SCK
SSEL FS
MISO DR(M)
MOSI DX(M)
The register addresses of the SSP controllers are shown in
offset
0x000
0x004
0x008
0x00C
0x010
0x014
SSI
CLK
DX(S)
DR(S)
Description
Control Register 0. Selects the serial clock rate, bus type, and data size. 0
Control Register 1. Selects master/slave and other modes.
Data Register. Writes fill the transmit FIFO, and reads empty the receive
FIFO.
Status Register
Clock Prescale Register
Interrupt Mask Set and Clear Register
Microwire
SK
CS
SI(M)
SO(S)
SO(M)
SI(S)
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Pin description
Serial Clock. SCK/CLK/SK is a clock signal used to synchronize the
transfer of data. It is driven by the master and received by the slave.
When the SPI interface is used, the clock is programmable to be
active-high or active-low, otherwise it is always active-high. SCK1 only
switches during a data transfer. Any other time, the SSPn interface
either holds it in its inactive state, or does not drive it (leaves it in
high-impedance state).
Frame Sync/Slave Select. When the SSPn interface is a bus master,
it drives this signal to an active state before the start of serial data, and
then releases it to an inactive state after the serial data has been sent.
The active state of this signal can be high or low depending upon the
selected bus and mode. When the SSPn is a bus slave, this signal
qualifies the presence of data from the Master, according to the
protocol in use.
When there is just one bus master and one bus slave, the Frame Sync
or Slave Select signal from the Master can be connected directly to the
slave's corresponding input. When there is more than one slave on the
bus, further qualification of their Frame Select/Slave Select inputs will
typically be necessary to prevent more than one slave from responding
to a transfer.
Master In Slave Out. The MISO signal transfers serial data from the
slave to the master. When the SSPn is a slave, serial data is output on
this signal. When the SSPn is a master, it clocks in serial data from this
signal. When the SSPn is a slave and is not selected by FS/SSEL, it
does not drive this signal (leaves it in high-impedance state).
Master Out Slave In. The MOSI signal transfers serial data from the
master to the slave. When the SSPn is a master, it outputs serial data
on this signal. When the SSPn is a slave, it clocks in serial data from
this signal.
Chapter 34: LPC18xx SSP0/1
Table 714
UM10430
and
© NXP B.V. 2011. All rights reserved.
Table
771 of 1164
Reset
value
0
0
0x0000
0003
0
0
715.
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