LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 720

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
32.5.6.1 DMA Operation
32.5.7 UART Line Control Register
Table 671. UART FIFO Control Register Write Only (FCR - addresses 0x4008 1008 (UART0),
The user can optionally operate the UART transmit and/or receive using DMA. The DMA
mode is determined by the DMA Mode Select bit in the FCR register. Note that for DMA
operation as for any operation of the UART, the FIFOs must be enabled via the FIFO
Enable bit in the FCR register.
UART receiver DMA
In DMA mode, the receiver DMA request is asserted when the receiver FIFO level
becomes equal to or greater than trigger level, or if a character time-out occurs. See the
description of the RX Trigger Level above. The receiver DMA request is cleared by the
DMA controller.
UART transmitter DMA
In DMA mode, the transmitter DMA request is asserted when the transmitter FIFO
transitions to not full. The transmitter DMA request is cleared by the DMA controller.
The LCR determines the format of the data character that is to be transmitted or received.
Table 672. UART Line Control Register (LCR - addresses 0x4008 100C (UART0), 0x400C
Bit
7:6
31:8 -
Bit
1:0
2
Symbol Value Description
WLS
SBS
Symbol
RXTRIG
LVL
0x400C 1008 (UART2), 0x400C 2008 (UART3)) bit description
100C (UART2), 0x400C 200C (UART3)) bit description
0x0
0x1
0x2
0x3
0
1
All information provided in this document is subject to legal disclaimers.
Value Description
-
0x0
0x1
0x2
0x3
Word Length Select.
5-bit character length.
6-bit character length.
7-bit character length.
8-bit character length.
Stop Bit Select.
1 stop bit.
2 stop bits (1.5 if LCR[1:0]=00).
Rev. 00.13 — 20 July 2011
RX Trigger Level.
These two bits determine how many receiver UART FIFO
characters must be written before an interrupt is activated.
Trigger level 0 (1 character or 0x01).
Trigger level 1 (4 characters or 0x04).
Trigger level 2 (8 characters or 0x08).
Trigger level 3 (14 characters or 0x0E).
Reserved
Chapter 32: LPC18xx USART0_2_3
UM10430
© NXP B.V. 2011. All rights reserved.
720 of 1164
Reset
value
0
-
Reset
Value
0
0