LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 516

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
22.8.1.1 Host bus burst access
22.8.1.2 Host data buffer alignment
The Transmit and Receive engines enter the Running state and attempt to acquire
descriptors from the respective descriptor lists. The Receive and Transmit engines then
begin processing Receive and Transmit operations. The Transmit and Receive processes
are independent of each other and can be started or stopped separately.
The DMA attempts to execute fixed-length Burst transfers on the AHB Master interface if
configured to do so (FB bit of DMA Register 0). The maximum Burst length is indicated
and limited by the PBL field (DMA Register 0[13:8]). The Receive and Transmit
descriptors are always accessed in the maximum possible (limited by PBL or 16 x 8/bus
width) burst-size for the 16-bytes to be read.
The Transmit DMA initiates a data transfer only when sufficient space to accommodate
the configured burst is available in MTL Transmit FIFO or the number of bytes till the end
of frame (when it is less than the configured burst-length). The DMA indicates the start
address and the number of transfers required to the AHB Master Interface. When the AHB
Interface is configured for fixed-length burst, then it transfers data using the best
combination of INCR4/8/16 and SINGLE transactions. Otherwise (no fixed-length burst), it
transfers data using INCR (undefined length) and SINGLE transactions.
The Receive DMA initiates a data transfer only when sufficient data to accommodate the
configured burst is available in MTL Receive FIFO or when the end of frame (when it is
less than the configured burst-length) is detected in the Receive FIFO. The DMA indicates
the start address and the number of transfers required to the AHB Master Interface. When
the AHB Interface is configured for fixed-length burst, then it transfers data using the best
combination of INCR4/8/16 and SINGLE transactions. If the end-of frame is reached
before the fixed-burst ends on the AHB interface, then dummy transfers are performed in
order to complete the fixed-burst. Otherwise (FB bit of DMA Register
transfers data using INCR (undefined length) and SINGLE transactions.
When the AHB interface is configured for address-aligned beats, both DMA engines
ensure that the first burst transfer the AHB initiates is less than or equal to the size of the
configured PBL. Thus, all subsequent beats start at an address that is aligned to the
configured PBL. The DMA can only align the address for beats up to size 16 (for PBL >
16), because the AHB interface does not support more than INCR16.
The Transmit and Receive data buffers do not have any restrictions on start address
alignment. For example, in systems with 32-bit memory, the start address for the buffers
can be aligned to any of the four bytes. However, the DMA always initiates transfers with
address aligned to the bus width with dummy data for the byte lanes not required. This
typically happens during the transfer of the beginning or end of an Ethernet frame.
5. Write to MAC Register
6. Write to DMA Register
7. Write to MAC Register
transmit operation (bit 3: Transmitter Enable). The PS and DM bits are set based on
the auto-negotiation result (read from the PHY).
reception.
Enable).
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 403
Table 428
Table 403
to configure the operating mode and enable the
to set bits 13 and 1 to start transmission and
to enable the Receive operation (bit 2: Receiver
Chapter 22: LPC18xx Ethernet
Table 421
UM10430
© NXP B.V. 2011. All rights reserved.
is reset), it
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