LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 206

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
13.4.3 ADC0 function select register
Table 112. Pin configuration for high drive pins P0_n to PF_n and CLK0 to CLK3 registers
For pins which have digital and analog functions, this register selects the input channel of
the ADC0 over any of the possible digital functions. This option is not available for channel
ADC0_7.
In addition, each analog function is pinned out on a dedicated analog pin which is not
affected by this register.
The following pins are controlled by the ENAIO0 register:
Bit
2:0
3
4
5
6
7
9:8
31:10
Symbol
MODE
EPD
EPUN
EHS
EZI
-
EHD
-
(SFS, address 0x4008 6000 (SFSP0_0) to 0x4008 6C0C (SFSCLK3) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0
1
0
1
0
1
0
1
0x0
0x1
0x2
0x3
Description
Select pin function
Function 0 (default)
Function 1
Function 2
Function 3
Function 4
Function 5
Function 6
Function 7
Enable pull-down resistor at pad
Disable pull-down.
Enable pull-down.
Disable pull-up resistor at pad. By default,
the pull-up resistor is enabled at reset.
Enable pull-up
Disable pull-up
Slew rate
Slow
Fast
Input buffer enable. The input buffer is
disabled by default at reset but must be
enabled to transfer data from the I/O buffer to
the pad.
Disable input buffer
Enable input buffer
Reserved
Select drive strength
Standard drive: 4 mA drive strength
Medium drive: 8 mA drive strength
High drive: 14 mA drive strength
Ultra-high drive: 20 mA drive strength
Reserved
Chapter 13: LPC18xx System Control Unit (SCU)
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
-
0
-
206 of 1164
-
Access
R/W
R/W
R/W
R/W
R/W
-
R/W