LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 953

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 891. Interrupt Active Bit Register 0 (IABR0 - address 0xE000 E300) bit description
<Document ID>
User manual
Bit
28
29
30
31:
30
Symbol
IAB_I2S
IAB_AES
IAB_SPIFI
-
42.1.8.6 Interrupt Priority Register 0
42.1.8.7 Interrupt Priority Register 1
Description
I2S interrupt active.
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
AES interrupt active.
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
SPIFI interrupt active.
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
Reserved.
The IPR0 register controls the priority of the first 4 peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
Table 892. Interrupt Priority Register 0 (IPR0 - address 0xE000 E400) bit description
The IPR1 register controls the priority of the second group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 893. Interrupt Priority Register 1 (IPR1 - address 0xE000 E404) bit
Bit
2:0
7:3
10:8
15:11 IP_ER
18:16 -
23:19 IP_DMA
26:24 -
31:27 -
Bit
2:0
7:3
10:8
15:11 IP_ETHER
18:16 -
Symbol
-
IP_DAC
-
Symbol
-
-
-
NET
description
All information provided in this document is subject to legal disclaimers.
Description
Reserved.These bits ignore writes, and read as 0.
Reserved.
Reserved.These bits ignore writes, and read as 0.
ETHERNET interrupt priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
Reserved.These bits ignore writes, and read as 0.
Rev. 00.13 — 20 July 2011
Description
Reserved. These bits ignore writes, and read as 0.
DAC interrupt priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
Reserved.These bits ignore writes, and read as 0.
Event router interrupt priority. 0 = highest priority. 31 (0x1F) =
lowest priority.
These bits ignore writes, and read as 0.
DMA interrupt priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
Reserved.These bits ignore writes, and read as 0.
Reserved.
…continued
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
Reset
value
0
0
0
0
0
0
0
-
Reset
value
0
0
0
0
0